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authorMaciej W. Rozycki <macro@linux-mips.org>2014-11-21 17:10:08 +0300
committerDavid S. Miller <davem@davemloft.net>2014-11-22 00:37:13 +0300
commit4d0438e56a8f9a1a18ba31bd53b9dc67af224980 (patch)
tree2658bdb4bef662c7febf304de65b6bd15a05dd32 /drivers/net/fddi/defxx.h
parent6a931423c918633d4d0cda96df042d7e44ad06b0 (diff)
downloadlinux-4d0438e56a8f9a1a18ba31bd53b9dc67af224980.tar.xz
defxx: Clean up DEFEA resource management
Reserve DEFEA resources according to actual use. There are three regions, for the ESIC ASIC's CSRs, for the discrete Burst Holdoff register, and for the PDQ ASIC's CSRs. The latter is mapped in the memory or port I/O address space depending on configuration. The two formers are hardwired and always mapped in the port I/O address space. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/fddi/defxx.h')
-rw-r--r--drivers/net/fddi/defxx.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/net/fddi/defxx.h b/drivers/net/fddi/defxx.h
index 16fe8049b238..9d30fde2ef3c 100644
--- a/drivers/net/fddi/defxx.h
+++ b/drivers/net/fddi/defxx.h
@@ -1481,9 +1481,11 @@ typedef union
#define PI_ESIC_K_CSR_IO_LEN 0x40 /* 64 bytes */
#define PI_ESIC_K_BURST_HOLDOFF_LEN 0x04 /* 4 bytes */
+#define PI_ESIC_K_ESIC_CSR_LEN 0x40 /* 64 bytes */
#define PI_DEFEA_K_CSR_IO 0x000
#define PI_DEFEA_K_BURST_HOLDOFF 0x040
+#define PI_ESIC_K_ESIC_CSR 0xC80
#define PI_ESIC_K_SLOT_ID 0xC80
#define PI_ESIC_K_SLOT_CNTRL 0xC84