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authorJacob Keller <jacob.e.keller@intel.com>2021-10-13 18:55:58 +0300
committerTony Nguyen <anthony.l.nguyen@intel.com>2021-12-21 20:11:40 +0300
commitb111ab5a11eb8f7261940c95ada9fbf5ca784731 (patch)
tree56a84387319e7021c1ada53ed10767fe4cc61c06 /drivers/net/ethernet/intel/ice/ice_ptp_hw.h
parent3a7496234d179a7dd6a7bb152f62422c3f38e15a (diff)
downloadlinux-b111ab5a11eb8f7261940c95ada9fbf5ca784731.tar.xz
ice: ensure the hardware Clock Generation Unit is configured
The E822 device has a Clock Generation Unit (CGU) responsible for determining the clock frequency that drives the timers. Ensure this function is initialized when bringing up the PTP support, so that the clock has a known frequency. Signed-off-by: Jacob Keller <jacob.e.keller@intel.com> Tested-by: Gurucharan G <gurucharanx.g@intel.com> Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
Diffstat (limited to 'drivers/net/ethernet/intel/ice/ice_ptp_hw.h')
-rw-r--r--drivers/net/ethernet/intel/ice/ice_ptp_hw.h20
1 files changed, 20 insertions, 0 deletions
diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.h b/drivers/net/ethernet/intel/ice/ice_ptp_hw.h
index 2b6613a56c40..70b1aff14225 100644
--- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.h
+++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.h
@@ -92,6 +92,26 @@ struct ice_vernier_info_e822 {
u32 rx_fixed_delay;
};
+/**
+ * struct ice_cgu_pll_params_e822
+ * @refclk_pre_div: Reference clock pre-divisor
+ * @feedback_div: Feedback divisor
+ * @frac_n_div: Fractional divisor
+ * @post_pll_div: Post PLL divisor
+ *
+ * Clock Generation Unit parameters used to program the PLL based on the
+ * selected TIME_REF frequency.
+ */
+struct ice_cgu_pll_params_e822 {
+ u32 refclk_pre_div;
+ u32 feedback_div;
+ u32 frac_n_div;
+ u32 post_pll_div;
+};
+
+extern const struct
+ice_cgu_pll_params_e822 e822_cgu_params[NUM_ICE_TIME_REF_FREQ];
+
/* Table of constants related to possible TIME_REF sources */
extern const struct ice_time_ref_info_e822 e822_time_ref[NUM_ICE_TIME_REF_FREQ];