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authorBruce Allan <bruce.w.allan@intel.com>2013-02-20 08:06:43 +0400
committerJeff Kirsher <jeffrey.t.kirsher@intel.com>2013-03-08 13:53:29 +0400
commit3ffcf2cb1e1b68eb48011158a023ee1d0bb4b1fc (patch)
tree3ba564ba06eca932cc36e8aec572b80969eacf01 /drivers/net/ethernet/intel/e1000e/defines.h
parentbbf441271b3c0e631f3687fef398c8a47fe0e3cd (diff)
downloadlinux-3ffcf2cb1e1b68eb48011158a023ee1d0bb4b1fc.tar.xz
e1000e: cleanup - move defines to appropriate header file
Signed-off-by: Bruce Allan <bruce.w.allan@intel.com> Tested-by: Aaron Brown <aaron.f.brown@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Diffstat (limited to 'drivers/net/ethernet/intel/e1000e/defines.h')
-rw-r--r--drivers/net/ethernet/intel/e1000e/defines.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/net/ethernet/intel/e1000e/defines.h b/drivers/net/ethernet/intel/e1000e/defines.h
index e6fe09096c34..b7c664f2a95f 100644
--- a/drivers/net/ethernet/intel/e1000e/defines.h
+++ b/drivers/net/ethernet/intel/e1000e/defines.h
@@ -216,6 +216,8 @@
#define E1000_CTRL_MEHE 0x00080000 /* Memory Error Handling Enable */
#define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */
#define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */
+#define E1000_CTRL_ADVD3WUC 0x00100000 /* D3 WUC */
+#define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000 /* PHY PM enable */
#define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */
#define E1000_CTRL_RST 0x04000000 /* Global reset */
#define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */
@@ -310,6 +312,7 @@
/* SerDes Control */
#define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400
+#define E1000_SCTL_ENABLE_SERDES_LOOPBACK 0x0410
/* Receive Checksum Control */
#define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */