diff options
author | Ansuel Smith <ansuelsmth@gmail.com> | 2021-10-14 01:39:19 +0300 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2021-10-15 13:06:38 +0300 |
commit | fd0bb28c547f7c8affb1691128cece38f5b626a1 (patch) | |
tree | 84196f632cf709c294651cb47338d6f51f8f8a80 /drivers/net/dsa/qca8k.c | |
parent | cef08115846e581f80ff99abf7bf218da1840616 (diff) | |
download | linux-fd0bb28c547f7c8affb1691128cece38f5b626a1.tar.xz |
net: dsa: qca8k: move port config to dedicated struct
Move ports related config to dedicated struct to keep things organized.
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/dsa/qca8k.c')
-rw-r--r-- | drivers/net/dsa/qca8k.c | 26 |
1 files changed, 13 insertions, 13 deletions
diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c index 296633147f46..bf58d4d1ae9b 100644 --- a/drivers/net/dsa/qca8k.c +++ b/drivers/net/dsa/qca8k.c @@ -1019,7 +1019,7 @@ qca8k_parse_port_config(struct qca8k_priv *priv) delay = 3; } - priv->rgmii_tx_delay[cpu_port_index] = delay; + priv->ports_config.rgmii_tx_delay[cpu_port_index] = delay; delay = 0; @@ -1035,7 +1035,7 @@ qca8k_parse_port_config(struct qca8k_priv *priv) delay = 3; } - priv->rgmii_rx_delay[cpu_port_index] = delay; + priv->ports_config.rgmii_rx_delay[cpu_port_index] = delay; /* Skip sgmii parsing for rgmii* mode */ if (mode == PHY_INTERFACE_MODE_RGMII || @@ -1045,17 +1045,17 @@ qca8k_parse_port_config(struct qca8k_priv *priv) break; if (of_property_read_bool(port_dn, "qca,sgmii-txclk-falling-edge")) - priv->sgmii_tx_clk_falling_edge = true; + priv->ports_config.sgmii_tx_clk_falling_edge = true; if (of_property_read_bool(port_dn, "qca,sgmii-rxclk-falling-edge")) - priv->sgmii_rx_clk_falling_edge = true; + priv->ports_config.sgmii_rx_clk_falling_edge = true; if (of_property_read_bool(port_dn, "qca,sgmii-enable-pll")) { - priv->sgmii_enable_pll = true; + priv->ports_config.sgmii_enable_pll = true; if (priv->switch_id == QCA8K_ID_QCA8327) { dev_err(priv->dev, "SGMII PLL should NOT be enabled for qca8327. Aborting enabling"); - priv->sgmii_enable_pll = false; + priv->ports_config.sgmii_enable_pll = false; } if (priv->switch_revision < 2) @@ -1281,15 +1281,15 @@ qca8k_mac_config_setup_internal_delay(struct qca8k_priv *priv, int cpu_port_inde * not enabled. With ID or TX/RXID delay is enabled and set * to the default and recommended value. */ - if (priv->rgmii_tx_delay[cpu_port_index]) { - delay = priv->rgmii_tx_delay[cpu_port_index]; + if (priv->ports_config.rgmii_tx_delay[cpu_port_index]) { + delay = priv->ports_config.rgmii_tx_delay[cpu_port_index]; val |= QCA8K_PORT_PAD_RGMII_TX_DELAY(delay) | QCA8K_PORT_PAD_RGMII_TX_DELAY_EN; } - if (priv->rgmii_rx_delay[cpu_port_index]) { - delay = priv->rgmii_rx_delay[cpu_port_index]; + if (priv->ports_config.rgmii_rx_delay[cpu_port_index]) { + delay = priv->ports_config.rgmii_rx_delay[cpu_port_index]; val |= QCA8K_PORT_PAD_RGMII_RX_DELAY(delay) | QCA8K_PORT_PAD_RGMII_RX_DELAY_EN; @@ -1397,7 +1397,7 @@ qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, val |= QCA8K_SGMII_EN_SD; - if (priv->sgmii_enable_pll) + if (priv->ports_config.sgmii_enable_pll) val |= QCA8K_SGMII_EN_PLL | QCA8K_SGMII_EN_RX | QCA8K_SGMII_EN_TX; @@ -1425,10 +1425,10 @@ qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, val = 0; /* SGMII Clock phase configuration */ - if (priv->sgmii_rx_clk_falling_edge) + if (priv->ports_config.sgmii_rx_clk_falling_edge) val |= QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE; - if (priv->sgmii_tx_clk_falling_edge) + if (priv->ports_config.sgmii_tx_clk_falling_edge) val |= QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE; if (val) |