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| author | Jiri Pirko <jiri@nvidia.com> | 2024-10-30 11:11:57 +0300 |
|---|---|---|
| committer | Jakub Kicinski <kuba@kernel.org> | 2024-11-03 19:39:07 +0300 |
| commit | e2017f27b6f888fb4ebc5c9a6d984bbf2f8b99ff (patch) | |
| tree | 0e2e4e44c21a6e494893e858ad22ebc0b47c0355 /drivers/net/dsa/dsa_loop.c | |
| parent | a1afb959add1fad43cb337448c244ed70bac3109 (diff) | |
| download | linux-e2017f27b6f888fb4ebc5c9a6d984bbf2f8b99ff.tar.xz | |
net/mlx5: DPLL, Add clock quality level op implementation
Use MSECQ register to query clock quality from firmware. Implement the
dpll op and fill-up the quality level value properly.
Reviewed-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
Signed-off-by: Jiri Pirko <jiri@nvidia.com>
Link: https://patch.msgid.link/20241030081157.966604-3-jiri@resnulli.us
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Diffstat (limited to 'drivers/net/dsa/dsa_loop.c')
0 files changed, 0 insertions, 0 deletions