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authorWill Deacon <will.deacon@arm.com>2019-04-12 15:42:18 +0300
committerWill Deacon <will.deacon@arm.com>2019-04-23 15:34:17 +0300
commit9726840d9cf0d42377e1591263d7c1d9ae0988ac (patch)
tree89db071594101bfbfbd70ac1cf7fca4f6d3ca47e /drivers/mtd/nand/raw/meson_nand.c
parent0cde62a46e88499cf3f62e3682248a3489488f08 (diff)
downloadlinux-9726840d9cf0d42377e1591263d7c1d9ae0988ac.tar.xz
docs/memory-barriers.txt: Update I/O section to be clearer about CPU vs thread
The revised I/O ordering section of memory-barriers.txt introduced in 4614bbdee357 ("docs/memory-barriers.txt: Rewrite "KERNEL I/O BARRIER EFFECTS" section") loosely refers to "the CPU", whereas the ordering guarantees generally apply within a thread of execution that can migrate between cores, with the scheduler providing the relevant barrier semantics. Reword the section to refer to "CPU thread" and call out ordering of MMIO writes separately from ordering of writes to memory. Ben also spotted that the string accessors are native-endian, so fix that up too. Link: https://lkml.kernel.org/r/080d1ec73e3e29d6ffeeeb50b39b613da28afb37.camel@kernel.crashing.org Fixes: 4614bbdee357 ("docs/memory-barriers.txt: Rewrite "KERNEL I/O BARRIER EFFECTS" section") Reported-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Will Deacon <will.deacon@arm.com>
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