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| author | Linus Torvalds <torvalds@linux-foundation.org> | 2025-09-12 02:35:06 +0300 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2025-09-12 02:35:06 +0300 |
| commit | 320475fbd590dc94a0a3d9173f81e0797ee1a232 (patch) | |
| tree | bc6b279e4bedd12370de1e6644d768a11de3ce9d /drivers/mtd/nand/raw/atmel/nand-controller.c | |
| parent | db87bd2ad1f736c2f7ab231f9b40c885934f6b2c (diff) | |
| parent | 4550d33e18112a11a740424c4eec063cd58e918c (diff) | |
| download | linux-320475fbd590dc94a0a3d9173f81e0797ee1a232.tar.xz | |
Merge tag 'mtd/fixes-for-6.17-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux
Pull mtd fixes from Miquel Raynal:
"SPI NAND fix:
- Wrong OOB layout for Winbond W25N01JW SPI NAND devices
Raw NAND fixes:
- Atmel raw NAND controller timings
- Buffer handling in stm32_fmc2 driver
- Error handling in Nuvoton's driver
MTD devices fixes:
- Wrong depends-on dependencies on the Intel DRM driver
* tag 'mtd/fixes-for-6.17-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux:
mtd: spinand: winbond: Fix oob_layout for W25N01JW
mtd: nand: raw: atmel: Respect tAR, tCLR in read setup timing
mtd: rawnand: stm32_fmc2: fix ECC overwrite
mtd: rawnand: stm32_fmc2: avoid overlapping mappings on ECC buffer
mtd: rawnand: nuvoton: Fix an error handling path in ma35_nand_chips_init()
mtd: MTD_INTEL_DG should depend on DRM_I915 or DRM_XE
Diffstat (limited to 'drivers/mtd/nand/raw/atmel/nand-controller.c')
| -rw-r--r-- | drivers/mtd/nand/raw/atmel/nand-controller.c | 16 |
1 files changed, 13 insertions, 3 deletions
diff --git a/drivers/mtd/nand/raw/atmel/nand-controller.c b/drivers/mtd/nand/raw/atmel/nand-controller.c index 84ab4a83cbd6..db94d14a3807 100644 --- a/drivers/mtd/nand/raw/atmel/nand-controller.c +++ b/drivers/mtd/nand/raw/atmel/nand-controller.c @@ -1378,13 +1378,23 @@ static int atmel_smc_nand_prepare_smcconf(struct atmel_nand *nand, return ret; /* + * Read setup timing depends on the operation done on the NAND: + * + * NRD_SETUP = max(tAR, tCLR) + */ + timeps = max(conf->timings.sdr.tAR_min, conf->timings.sdr.tCLR_min); + ncycles = DIV_ROUND_UP(timeps, mckperiodps); + totalcycles += ncycles; + ret = atmel_smc_cs_conf_set_setup(smcconf, ATMEL_SMC_NRD_SHIFT, ncycles); + if (ret) + return ret; + + /* * The read cycle timing is directly matching tRC, but is also * dependent on the setup and hold timings we calculated earlier, * which gives: * - * NRD_CYCLE = max(tRC, NRD_PULSE + NRD_HOLD) - * - * NRD_SETUP is always 0. + * NRD_CYCLE = max(tRC, NRD_SETUP + NRD_PULSE + NRD_HOLD) */ ncycles = DIV_ROUND_UP(conf->timings.sdr.tRC_min, mckperiodps); ncycles = max(totalcycles, ncycles); |