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authorRomain Izard <romain.izard.pro@gmail.com>2017-09-28 12:46:23 +0300
committerBoris Brezillon <boris.brezillon@free-electrons.com>2017-10-07 12:28:05 +0300
commit143b0ab97d7a40df399cfbc6e925107bed1c7953 (patch)
treec24127b71537b6d88468040c0cb47877ff57bb76 /drivers/mtd/nand/atmel/pmecc.h
parent8d6b6d7e135e9bbfc923d34a45cb0e72695e63ed (diff)
downloadlinux-143b0ab97d7a40df399cfbc6e925107bed1c7953.tar.xz
mtd: nand: atmel: Avoid ECC errors when leaving backup mode
During backup mode, the contents of all registers will be cleared as the SoC will be completely powered down. For a product that boots on NAND Flash memory, the bootloader will obviously use the related controller to read the Flash and correct any detected error in the memory, before handling back control to the kernel's resuming entry point. But it does not clean the NAND controller registers after use and on its side the kernel driver expects the error locator to be powered down and in a clean state. Add a resume hook for the PMECC error locator, and reset its registers. Signed-off-by: Romain Izard <romain.izard.pro@gmail.com> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Diffstat (limited to 'drivers/mtd/nand/atmel/pmecc.h')
-rw-r--r--drivers/mtd/nand/atmel/pmecc.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/mtd/nand/atmel/pmecc.h b/drivers/mtd/nand/atmel/pmecc.h
index a8ddbfca2ea5..817e0dd9fd15 100644
--- a/drivers/mtd/nand/atmel/pmecc.h
+++ b/drivers/mtd/nand/atmel/pmecc.h
@@ -61,6 +61,7 @@ atmel_pmecc_create_user(struct atmel_pmecc *pmecc,
struct atmel_pmecc_user_req *req);
void atmel_pmecc_destroy_user(struct atmel_pmecc_user *user);
+void atmel_pmecc_reset(struct atmel_pmecc *pmecc);
int atmel_pmecc_enable(struct atmel_pmecc_user *user, int op);
void atmel_pmecc_disable(struct atmel_pmecc_user *user);
int atmel_pmecc_wait_rdy(struct atmel_pmecc_user *user);