diff options
| author | Tuomas Tynkkynen <ttynkkynen@nvidia.com> | 2013-06-11 14:11:19 +0400 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2013-06-18 03:46:06 +0400 |
| commit | 36dd68319c7b56a76ed450b0e470067b5d74b9b2 (patch) | |
| tree | a52728d996ead41a45953a3c6b585b8cdc32a85b /drivers/memory | |
| parent | d777f98bfa44e5a2748603276e9e9fb6ab999079 (diff) | |
| download | linux-36dd68319c7b56a76ed450b0e470067b5d74b9b2.tar.xz | |
memory: tegra30-mc: Fix IRQ handler.
In Tegra30 any memory controller interrupt would cause an infinite loop in the
IRQ handler. Additionally, a garbage pointer was used to read the MC
status registers, which causes wrong values to be printed if a MC error
occurred.
Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Thierry Reding <thierry.reding@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/memory')
| -rw-r--r-- | drivers/memory/tegra30-mc.c | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/drivers/memory/tegra30-mc.c b/drivers/memory/tegra30-mc.c index f4ae074badc3..58d2979b4035 100644 --- a/drivers/memory/tegra30-mc.c +++ b/drivers/memory/tegra30-mc.c @@ -218,7 +218,7 @@ static void tegra30_mc_decode(struct tegra30_mc *mc, int n) return; } - err = readl(mc + MC_ERR_STATUS); + err = mc_readl(mc, MC_ERR_STATUS); type = (err & MC_ERR_TYPE_MASK) >> MC_ERR_TYPE_SHIFT; perm = (err & MC_ERR_INVALID_SMMU_PAGE_MASK) >> @@ -235,7 +235,7 @@ static void tegra30_mc_decode(struct tegra30_mc *mc, int n) if (cid < ARRAY_SIZE(tegra30_mc_client)) client = tegra30_mc_client[cid]; - addr = readl(mc + MC_ERR_ADR); + addr = mc_readl(mc, MC_ERR_ADR); dev_err_ratelimited(mc->dev, "%s (0x%08x): 0x%08x %s (%s %s %s %s)\n", mc_int_err[idx], err, addr, client, @@ -313,8 +313,11 @@ static irqreturn_t tegra30_mc_isr(int irq, void *data) mask &= stat; if (!mask) return IRQ_NONE; - while ((bit = ffs(mask)) != 0) + while ((bit = ffs(mask)) != 0) { tegra30_mc_decode(mc, bit - 1); + mask &= ~BIT(bit - 1); + } + mc_writel(mc, stat, MC_INTSTATUS); return IRQ_HANDLED; } |