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authorSteve Wise <swise@opengridcomputing.com>2010-09-18 00:40:15 +0400
committerRoland Dreier <rolandd@cisco.com>2010-09-28 21:53:50 +0400
commit40dbf6ee381008e471d3c4a332971247b7799744 (patch)
tree6249fb3fd9cca9e2e42c01a798ef21b4f5a1e328 /drivers/infiniband/hw/cxgb4/provider.c
parent410ade4c26bdf256fea3246e968a12409eb08763 (diff)
downloadlinux-40dbf6ee381008e471d3c4a332971247b7799744.tar.xz
RDMA/cxgb4: Fastreg NSMR fixes
- Remove dsgl support - doesn't work in T4. - Wrap the immediate PBL as needed when building it in the wr. - Adjust max pbl depth allowed based on ulptx alignment requirements. - Bump the slots per SQ to 5 to allow up to 128MB fast registers. - Advertise fastreg support by default. Signed-off-by: Steve Wise <swise@opengridcomputing.com> Signed-off-by: Roland Dreier <rolandd@cisco.com>
Diffstat (limited to 'drivers/infiniband/hw/cxgb4/provider.c')
-rw-r--r--drivers/infiniband/hw/cxgb4/provider.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/infiniband/hw/cxgb4/provider.c b/drivers/infiniband/hw/cxgb4/provider.c
index a49a9c1275a3..81e127713675 100644
--- a/drivers/infiniband/hw/cxgb4/provider.c
+++ b/drivers/infiniband/hw/cxgb4/provider.c
@@ -54,9 +54,9 @@
#include "iw_cxgb4.h"
-static int fastreg_support;
+static int fastreg_support = 1;
module_param(fastreg_support, int, 0644);
-MODULE_PARM_DESC(fastreg_support, "Advertise fastreg support (default=0)");
+MODULE_PARM_DESC(fastreg_support, "Advertise fastreg support (default=1)");
static int c4iw_modify_port(struct ib_device *ibdev,
u8 port, int port_modify_mask,