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| author | George Stark <gnstark@sberdevices.ru> | 2023-06-06 19:53:57 +0300 |
|---|---|---|
| committer | Jonathan Cameron <Jonathan.Cameron@huawei.com> | 2023-06-10 20:57:51 +0300 |
| commit | c57fa0037024c92c2ca34243e79e857da5d2c0a9 (patch) | |
| tree | 2a0a033649c10eae33b8b9fed3bd824457cbd6e1 /drivers/iio/adc/ingenic-adc.c | |
| parent | b410a9307bc3a7cdee3c930c98f6fc9cf1d2c484 (diff) | |
| download | linux-c57fa0037024c92c2ca34243e79e857da5d2c0a9.tar.xz | |
meson saradc: fix clock divider mask length
According to the datasheets of supported meson SoCs length of ADC_CLK_DIV
field is 6-bit. Although all supported SoCs have the register
with that field documented later SoCs use external clock rather than
ADC internal clock so this patch affects only meson8 family (S8* SoCs).
Fixes: 3adbf3427330 ("iio: adc: add a driver for the SAR ADC found in Amlogic Meson SoCs")
Signed-off-by: George Stark <GNStark@sberdevices.ru>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Link: https://lore.kernel.org/r/20230606165357.42417-1-gnstark@sberdevices.ru
Cc: <stable@vger.kernel.org>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Diffstat (limited to 'drivers/iio/adc/ingenic-adc.c')
0 files changed, 0 insertions, 0 deletions