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| author | Mukul Joshi <mukul.joshi@amd.com> | 2025-02-26 23:29:09 +0300 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2025-12-08 22:12:05 +0300 |
| commit | 9c34a4c19efa8686737c03f1718618da58cae546 (patch) | |
| tree | 7c88f73cd48fb48a265caa26a61b90488cb025f7 /drivers/gpu | |
| parent | 1fee035bee8d99436cde73b5727c8a19ac9534b6 (diff) | |
| download | linux-9c34a4c19efa8686737c03f1718618da58cae546.tar.xz | |
drm/amdgpu: Fix golden register init for GFX 12.1.0
TCP_UTCL0 registers are not per XCD so don't init them on a per
XCD basis.
Fixes: ad5f1ee0a9b0 ("drm/amdgpu: Add initial support for gfx v12_1")
Signed-off-by: Mukul Joshi <mukul.joshi@amd.com>
Reviewed-by: Alex Sierra <alex.sierra@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c | 20 |
1 files changed, 8 insertions, 12 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c index b2702287536f..a16cd26e9a1b 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c @@ -2509,22 +2509,18 @@ static void gfx_v12_1_xcc_disable_gpa_mode(struct amdgpu_device *adev, static void gfx_v12_1_init_golden_registers(struct amdgpu_device *adev) { - int i, num_xcc; uint32_t val; - num_xcc = NUM_XCC(adev->gfx.xcc_mask); - for (i = 0; i < num_xcc; i++) { - /* Setup the TCP Thrashing control register */ - val = RREG32_SOC15(GC, GET_INST(GC, i), regTCP_UTCL0_THRASHING_CTRL); + /* Setup the TCP Thrashing control register */ + val = RREG32_SOC15(GC, 0, regTCP_UTCL0_THRASHING_CTRL); - val = REG_SET_FIELD(val, TCP_UTCL0_THRASHING_CTRL, THRASHING_EN, 0x2); - val = REG_SET_FIELD(val, TCP_UTCL0_THRASHING_CTRL, - RETRY_FRAGMENT_THRESHOLD_DOWN_EN, 0x0); - val = REG_SET_FIELD(val, TCP_UTCL0_THRASHING_CTRL, - RETRY_FRAGMENT_THRESHOLD_UP_EN, 0x0); + val = REG_SET_FIELD(val, TCP_UTCL0_THRASHING_CTRL, THRASHING_EN, 0x2); + val = REG_SET_FIELD(val, TCP_UTCL0_THRASHING_CTRL, + RETRY_FRAGMENT_THRESHOLD_DOWN_EN, 0x0); + val = REG_SET_FIELD(val, TCP_UTCL0_THRASHING_CTRL, + RETRY_FRAGMENT_THRESHOLD_UP_EN, 0x0); - WREG32_SOC15(GC, GET_INST(GC, i), regTCP_UTCL0_THRASHING_CTRL, val); - } + WREG32_SOC15(GC, 0, regTCP_UTCL0_THRASHING_CTRL, val); } static int gfx_v12_1_hw_init(struct amdgpu_ip_block *ip_block) |