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authorLucas Stach <l.stach@pengutronix.de>2024-05-17 13:45:48 +0300
committerPhilipp Zabel <p.zabel@pengutronix.de>2024-06-26 18:43:54 +0300
commit4dbc7d5d61d5212bcfef794f47562ace58ac390b (patch)
treef30b30231156ccdc226169d9b3907394ad2eac6f /drivers/gpu/ipu-v3/ipu-prg.c
parentee7ff5e26b9d915667db75a2c79b04590afe3b80 (diff)
downloadlinux-4dbc7d5d61d5212bcfef794f47562ace58ac390b.tar.xz
gpu: ipu-v3: pre: add dynamic buffer layout reconfiguration
imx-drm doesn't mandate a modeset when the framebuffer modifier changes, but currently the tile prefetch and resolve (TPR) configuration of the PRE is only set up on the initial modeset. As the TPR configuration is double buffered, same as all the other PRE states, we can support dynamic reconfiguration of the buffer layout from one frame to another. As switching between (super-)tiled and linear prefetch needs to touch the CTRL register make sure to do the reconfiguration inside the safe window. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/20240517104549.3648939-2-l.stach@pengutronix.de Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://patchwork.freedesktop.org/patch/msgid/20240517104549.3648939-2-l.stach@pengutronix.de
Diffstat (limited to 'drivers/gpu/ipu-v3/ipu-prg.c')
-rw-r--r--drivers/gpu/ipu-v3/ipu-prg.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/ipu-v3/ipu-prg.c b/drivers/gpu/ipu-v3/ipu-prg.c
index 729605709955..661dedf6617a 100644
--- a/drivers/gpu/ipu-v3/ipu-prg.c
+++ b/drivers/gpu/ipu-v3/ipu-prg.c
@@ -287,7 +287,7 @@ int ipu_prg_channel_configure(struct ipuv3_channel *ipu_chan,
chan = &prg->chan[prg_chan];
if (chan->enabled) {
- ipu_pre_update(prg->pres[chan->used_pre], *eba);
+ ipu_pre_update(prg->pres[chan->used_pre], modifier, *eba);
return 0;
}