diff options
| author | Thierry Reding <treding@nvidia.com> | 2014-12-02 17:15:06 +0300 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2015-01-27 12:14:46 +0300 |
| commit | c5a107d3279734c3599136696b6790add9e8e798 (patch) | |
| tree | ee21148385dc034bc49247b7678641032de09b21 /drivers/gpu/drm/tegra/dc.c | |
| parent | d5bae6f33ee98cf4c6939c4b8db2fc76c1eed720 (diff) | |
| download | linux-c5a107d3279734c3599136696b6790add9e8e798.tar.xz | |
drm/tegra: Add tegra_dc_setup_clock() helper
This is a small helper that performs the basic steps required by all
output drivers to prepare the display controller for use with a given
encoder.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/gpu/drm/tegra/dc.c')
| -rw-r--r-- | drivers/gpu/drm/tegra/dc.c | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c index e35e10758556..90909883e739 100644 --- a/drivers/gpu/drm/tegra/dc.c +++ b/drivers/gpu/drm/tegra/dc.c @@ -1092,6 +1092,26 @@ static int tegra_crtc_setup_clk(struct drm_crtc *crtc, return 0; } +int tegra_dc_setup_clock(struct tegra_dc *dc, struct clk *parent, + unsigned long pclk, unsigned int div) +{ + u32 value; + int err; + + err = clk_set_parent(dc->clk, parent); + if (err < 0) { + dev_err(dc->dev, "failed to set parent clock: %d\n", err); + return err; + } + + DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc->clk), div); + + value = SHIFT_CLK_DIVIDER(div) | PIXEL_CLK_DIVIDER_PCD1; + tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL); + + return 0; +} + static int tegra_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode, struct drm_display_mode *adjusted, |