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| author | Maxime Ripard <maxime.ripard@bootlin.com> | 2019-02-11 17:41:22 +0300 |
|---|---|---|
| committer | Maxime Ripard <maxime.ripard@bootlin.com> | 2019-02-19 13:08:17 +0300 |
| commit | 85fb352666732a9e5caf6027b9c253b3d7881d8f (patch) | |
| tree | 7062a7c5d62700de48af9833abc5c298fb0c9730 /drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h | |
| parent | fd347df16d4ed2eef565344b8f16a1134bddf185 (diff) | |
| download | linux-85fb352666732a9e5caf6027b9c253b3d7881d8f.tar.xz | |
drm/sun4i: dsi: Restrict DSI tcon clock divider
The current code allows the TCON clock divider to have a range between 4
and 127 when feeding the DSI controller.
The only display supported so far had a display clock rate that ended up
using a divider of 4, but testing with other displays show that only 4
seems to be functional.
This also aligns with what Allwinner is doing in their BSP, so let's just
hardcode that we want a divider of 4 when using the DSI output.
Reviewed-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Link: https://patchwork.freedesktop.org/patch/msgid/074e88ae472f5e0492e26939c74b44fb4125ffbd.1549896081.git-series.maxime.ripard@bootlin.com
Diffstat (limited to 'drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h')
| -rw-r--r-- | drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h index a07090579f84..5c3ad5be0690 100644 --- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h +++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h @@ -13,6 +13,8 @@ #include <drm/drm_encoder.h> #include <drm/drm_mipi_dsi.h> +#define SUN6I_DSI_TCON_DIV 4 + struct sun6i_dsi { struct drm_connector connector; struct drm_encoder encoder; |