diff options
| author | Thomas Zimmermann <tzimmermann@suse.de> | 2023-03-13 12:14:05 +0300 |
|---|---|---|
| committer | Thomas Zimmermann <tzimmermann@suse.de> | 2023-03-13 12:14:05 +0300 |
| commit | b3c9a04135bdbd3aabd5e9534bad0fe6df505f8a (patch) | |
| tree | 2372cd098db2a0e45da99125258e454b827cb577 /drivers/gpu/drm/rcar-du/rcar_du_regs.h | |
| parent | fe9ae05cfbe587dda724fcf537c00bc2f287da62 (diff) | |
| parent | eeac8ede17557680855031c6f305ece2378af326 (diff) | |
| download | linux-b3c9a04135bdbd3aabd5e9534bad0fe6df505f8a.tar.xz | |
Merge drm/drm-fixes into drm-misc-fixes
Backmerging to get latest upstream.
Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
Diffstat (limited to 'drivers/gpu/drm/rcar-du/rcar_du_regs.h')
| -rw-r--r-- | drivers/gpu/drm/rcar-du/rcar_du_regs.h | 8 |
1 files changed, 2 insertions, 6 deletions
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_regs.h b/drivers/gpu/drm/rcar-du/rcar_du_regs.h index c1bcb0e8b5b4..789ae9285108 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_regs.h +++ b/drivers/gpu/drm/rcar-du/rcar_du_regs.h @@ -283,12 +283,8 @@ #define DPLLCR 0x20044 #define DPLLCR_CODE (0x95 << 24) #define DPLLCR_PLCS1 (1 << 23) -/* - * PLCS0 is bit 21, but H3 ES1.x requires bit 20 to be set as well. As bit 20 - * isn't implemented by other SoC in the Gen3 family it can safely be set - * unconditionally. - */ -#define DPLLCR_PLCS0 (3 << 20) +#define DPLLCR_PLCS0_PLL (1 << 21) +#define DPLLCR_PLCS0_H3ES1X_PLL1 (1 << 20) #define DPLLCR_CLKE (1 << 18) #define DPLLCR_FDPLL(n) ((n) << 12) #define DPLLCR_N(n) ((n) << 5) |