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authorAlex Deucher <alexander.deucher@amd.com>2012-09-13 01:39:57 +0400
committerAlex Deucher <alexander.deucher@amd.com>2012-09-20 21:10:44 +0400
commit9dbbcfc6894957fdbb311ba92c85c026659878b5 (patch)
tree1e0727929dbc39929f53d8a70e6a1df5c3833c37 /drivers/gpu/drm/radeon/atombios_crtc.c
parentf3dd8508d459a2d0d0bc426144b92f1696d4fe86 (diff)
downloadlinux-9dbbcfc6894957fdbb311ba92c85c026659878b5.tar.xz
drm/radeon/dce3: use a single PPLL for all DP displays
If possible, use a single PPLL for multiple DP displays on DCE3.x. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/atombios_crtc.c')
-rw-r--r--drivers/gpu/drm/radeon/atombios_crtc.c24
1 files changed, 24 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index 8e73d53b769e..c5a040677d48 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -1652,6 +1652,30 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc)
return ATOM_PPLL1;
DRM_ERROR("unable to allocate a PPLL\n");
return ATOM_PPLL_INVALID;
+ } else if (ASIC_IS_DCE3(rdev)) {
+ list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
+ if (test_encoder->crtc && (test_encoder->crtc == crtc)) {
+ /* in DP mode, the DP ref clock can come from either PPLL
+ * depending on the asic:
+ * DCE3: PPLL1 or PPLL2
+ */
+ if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_encoder))) {
+ /* use the same PPLL for all DP monitors */
+ pll = radeon_get_shared_dp_ppll(crtc);
+ if (pll != ATOM_PPLL_INVALID)
+ return pll;
+ }
+ break;
+ }
+ }
+ /* all other cases */
+ pll_in_use = radeon_get_pll_use_mask(crtc);
+ if (!(pll_in_use & (1 << ATOM_PPLL2)))
+ return ATOM_PPLL2;
+ if (!(pll_in_use & (1 << ATOM_PPLL1)))
+ return ATOM_PPLL1;
+ DRM_ERROR("unable to allocate a PPLL\n");
+ return ATOM_PPLL_INVALID;
} else
/* use PPLL1 or PPLL2 */
return radeon_crtc->crtc_id;