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authorTomi Valkeinen <tomi.valkeinen@ti.com>2016-05-27 13:49:05 +0300
committerTomi Valkeinen <tomi.valkeinen@ti.com>2017-04-03 12:36:40 +0300
commitd5e7efad7b34750942883997ff67e8afd4f883cc (patch)
treebd5e9a0a207d004bb2afb17be710cec83c658239 /drivers/gpu/drm/omapdrm
parent5f6ab8ca18f2cd7ece8626a31bd656e5e7bc9425 (diff)
downloadlinux-d5e7efad7b34750942883997ff67e8afd4f883cc.tar.xz
drm/omap: fix HDMI sync polarities
While implementing writeback support, odd behavior of WBDELAYCOUNT was observed with the combination of WB capture and HDMI. The result of the debugging was that the HDMI sync polarities are not set correctly. The current code sets the sync polarities going from HDMI WP to DISPC according to the video mode used, which seems to work normally fine, but causes problems with WB as WB expects the syncs to be active-high. This patch changes the HDMI sync polarities so that the DISPC always gets active-high syncs from HDMI WP, and the HDMI core gets sync polarities according to the used video mode. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Diffstat (limited to 'drivers/gpu/drm/omapdrm')
-rw-r--r--drivers/gpu/drm/omapdrm/dss/hdmi_wp.c12
1 files changed, 7 insertions, 5 deletions
diff --git a/drivers/gpu/drm/omapdrm/dss/hdmi_wp.c b/drivers/gpu/drm/omapdrm/dss/hdmi_wp.c
index b783d5a0750e..597ec9d87d1d 100644
--- a/drivers/gpu/drm/omapdrm/dss/hdmi_wp.c
+++ b/drivers/gpu/drm/omapdrm/dss/hdmi_wp.c
@@ -147,15 +147,17 @@ void hdmi_wp_video_config_interface(struct hdmi_wp_data *wp,
struct videomode *vm)
{
u32 r;
- bool vsync_pol, hsync_pol;
+ bool vsync_inv, hsync_inv;
DSSDBG("Enter hdmi_wp_video_config_interface\n");
- vsync_pol = !!(vm->flags & DISPLAY_FLAGS_VSYNC_HIGH);
- hsync_pol = !!(vm->flags & DISPLAY_FLAGS_HSYNC_HIGH);
+ vsync_inv = !!(vm->flags & DISPLAY_FLAGS_VSYNC_LOW);
+ hsync_inv = !!(vm->flags & DISPLAY_FLAGS_HSYNC_LOW);
r = hdmi_read_reg(wp->base, HDMI_WP_VIDEO_CFG);
- r = FLD_MOD(r, vsync_pol, 7, 7);
- r = FLD_MOD(r, hsync_pol, 6, 6);
+ r = FLD_MOD(r, 1, 7, 7); /* VSYNC_POL to dispc active high */
+ r = FLD_MOD(r, 1, 6, 6); /* HSYNC_POL to dispc active high */
+ r = FLD_MOD(r, vsync_inv, 5, 5); /* CORE_VSYNC_INV */
+ r = FLD_MOD(r, hsync_inv, 4, 4); /* CORE_HSYNC_INV */
r = FLD_MOD(r, !!(vm->flags & DISPLAY_FLAGS_INTERLACED), 3, 3);
r = FLD_MOD(r, 1, 1, 0); /* HDMI_TIMING_MASTER_24BIT */
hdmi_write_reg(wp->base, HDMI_WP_VIDEO_CFG, r);