diff options
| author | Jordan Crouse <jcrouse@codeaurora.org> | 2017-11-21 22:40:57 +0300 |
|---|---|---|
| committer | Rob Clark <robdclark@gmail.com> | 2018-01-10 16:58:42 +0300 |
| commit | c09513cfebd8d936a7aed3c0302104fb47a4a03a (patch) | |
| tree | 00def9b8aa3880725e4a494ba88139e104fb75a8 /drivers/gpu/drm/msm | |
| parent | f56d9df656c41b141399c1edbcc9b0ed048120c2 (diff) | |
| download | linux-c09513cfebd8d936a7aed3c0302104fb47a4a03a.tar.xz | |
drm/msm/adreno: a5xx: Explicitly program the CP0 performance counter
Even though the default countable for CP0 is CP_ALWAYS_COUNT (0),
program the selector during HW initialization in an effort to be
up front about which counters are programmed and why.
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
Diffstat (limited to 'drivers/gpu/drm/msm')
| -rw-r--r-- | drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c index fdbe9e9bb2b1..56c2c441fabf 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c @@ -597,6 +597,9 @@ static int a5xx_hw_init(struct msm_gpu *gpu) /* Turn on performance counters */ gpu_write(gpu, REG_A5XX_RBBM_PERFCTR_CNTL, 0x01); + /* Select CP0 to always count cycles */ + gpu_write(gpu, REG_A5XX_CP_PERFCTR_CP_SEL_0, PERF_CP_ALWAYS_COUNT); + /* Increase VFD cache access so LRZ and other data gets evicted less */ gpu_write(gpu, REG_A5XX_UCHE_CACHE_WAYS, 0x02); |