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| author | Jeykumar Sankaran <jsanka@codeaurora.org> | 2019-02-14 04:19:10 +0300 |
|---|---|---|
| committer | Rob Clark <robdclark@chromium.org> | 2019-04-18 20:04:10 +0300 |
| commit | b6057cda8f6cac5f50dbac7ff5ca825fdafdeb39 (patch) | |
| tree | 262596cdefc0f5e7bc97bf6ce8ef95ffde75311d /drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | |
| parent | f98baa3109cea46083d2361ab14a0207d1b1bd16 (diff) | |
| download | linux-b6057cda8f6cac5f50dbac7ff5ca825fdafdeb39.tar.xz | |
drm/msm/dpu: move hw_inf encoder baseclass
Both video and command physical encoders will have
a hw interface assigned to it. So there is really no
need to track the hw block in specific encoder subclass.
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Link: https://patchwork.freedesktop.org/patch/msgid/1550107156-17625-2-git-send-email-jsanka@codeaurora.org
Signed-off-by: Rob Clark <robdclark@chromium.org>
Diffstat (limited to 'drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h')
| -rw-r--r-- | drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h index db94f3d3bea3..66a1fd4b014c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h @@ -200,6 +200,7 @@ struct dpu_encoder_irq { * @hw_mdptop: Hardware interface to the top registers * @hw_ctl: Hardware interface to the ctl registers * @hw_pp: Hardware interface to the ping pong registers + * @hw_intf: Hardware interface to the intf registers * @dpu_kms: Pointer to the dpu_kms top level * @cached_mode: DRM mode cached at mode_set time, acted on in enable * @enabled: Whether the encoder has enabled and running a mode @@ -228,6 +229,7 @@ struct dpu_encoder_phys { struct dpu_hw_mdp *hw_mdptop; struct dpu_hw_ctl *hw_ctl; struct dpu_hw_pingpong *hw_pp; + struct dpu_hw_intf *hw_intf; struct dpu_kms *dpu_kms; struct drm_display_mode cached_mode; enum dpu_enc_split_role split_role; @@ -254,12 +256,10 @@ static inline int dpu_encoder_phys_inc_pending(struct dpu_encoder_phys *phys) * struct dpu_encoder_phys_vid - sub-class of dpu_encoder_phys to handle video * mode specific operations * @base: Baseclass physical encoder structure - * @hw_intf: Hardware interface to the intf registers * @timing_params: Current timing parameter */ struct dpu_encoder_phys_vid { struct dpu_encoder_phys base; - struct dpu_hw_intf *hw_intf; struct intf_timing_params timing_params; }; |