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author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2020-02-25 20:11:09 +0300 |
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committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2020-03-02 17:42:18 +0300 |
commit | 05e8155afe35c61c55bad39eaa7178d4aaa729c8 (patch) | |
tree | be15cf755d591dc5b22131d086f0011a79d15aee /drivers/gpu/drm/i915/intel_pm.c | |
parent | 06812bd9ac7c5aa3d53f1dbe0d24fd33c26a8d5f (diff) | |
download | linux-05e8155afe35c61c55bad39eaa7178d4aaa729c8.tar.xz |
drm/i915: Use a sentinel to terminate the dbuf slice arrays
Make life a bit simpler by sticking a sentinel at the end of
the dbuf slice arrays. This way we don't need to pass in the
size. Also unify the types (u8 vs. u32) for active_pipes.
Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200225171125.28885-5-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_pm.c')
-rw-r--r-- | drivers/gpu/drm/i915/intel_pm.c | 34 |
1 files changed, 13 insertions, 21 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index be24969e49d0..831e53c137cf 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3833,7 +3833,7 @@ static u16 intel_get_ddb_size(struct drm_i915_private *dev_priv) } static u8 skl_compute_dbuf_slices(const struct intel_crtc_state *crtc_state, - u32 active_pipes); + u8 active_pipes); static void skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv, @@ -4218,6 +4218,7 @@ static const struct dbuf_slice_conf_entry icl_allowed_dbufs[] = [PIPE_C] = BIT(DBUF_S2), }, }, + {} }; /* @@ -4340,16 +4341,15 @@ static const struct dbuf_slice_conf_entry tgl_allowed_dbufs[] = [PIPE_D] = BIT(DBUF_S2), }, }, + {} }; -static u8 compute_dbuf_slices(enum pipe pipe, - u32 active_pipes, - const struct dbuf_slice_conf_entry *dbuf_slices, - int size) +static u8 compute_dbuf_slices(enum pipe pipe, u8 active_pipes, + const struct dbuf_slice_conf_entry *dbuf_slices) { int i; - for (i = 0; i < size; i++) { + for (i = 0; i < dbuf_slices[i].active_pipes; i++) { if (dbuf_slices[i].active_pipes == active_pipes) return dbuf_slices[i].dbuf_mask[pipe]; } @@ -4361,8 +4361,7 @@ static u8 compute_dbuf_slices(enum pipe pipe, * returns correspondent DBuf slice mask as stated in BSpec for particular * platform. */ -static u32 icl_compute_dbuf_slices(enum pipe pipe, - u32 active_pipes) +static u8 icl_compute_dbuf_slices(enum pipe pipe, u8 active_pipes) { /* * FIXME: For ICL this is still a bit unclear as prev BSpec revision @@ -4376,32 +4375,25 @@ static u32 icl_compute_dbuf_slices(enum pipe pipe, * still here - we will need it once those additional constraints * pop up. */ - return compute_dbuf_slices(pipe, active_pipes, - icl_allowed_dbufs, - ARRAY_SIZE(icl_allowed_dbufs)); + return compute_dbuf_slices(pipe, active_pipes, icl_allowed_dbufs); } -static u32 tgl_compute_dbuf_slices(enum pipe pipe, - u32 active_pipes) +static u8 tgl_compute_dbuf_slices(enum pipe pipe, u8 active_pipes) { - return compute_dbuf_slices(pipe, active_pipes, - tgl_allowed_dbufs, - ARRAY_SIZE(tgl_allowed_dbufs)); + return compute_dbuf_slices(pipe, active_pipes, tgl_allowed_dbufs); } static u8 skl_compute_dbuf_slices(const struct intel_crtc_state *crtc_state, - u32 active_pipes) + u8 active_pipes) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum pipe pipe = crtc->pipe; if (IS_GEN(dev_priv, 12)) - return tgl_compute_dbuf_slices(pipe, - active_pipes); + return tgl_compute_dbuf_slices(pipe, active_pipes); else if (IS_GEN(dev_priv, 11)) - return icl_compute_dbuf_slices(pipe, - active_pipes); + return icl_compute_dbuf_slices(pipe, active_pipes); /* * For anything else just return one slice yet. * Should be extended for other platforms. |