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| author | Michal Wajdeczko <michal.wajdeczko@intel.com> | 2018-03-28 00:41:24 +0300 |
|---|---|---|
| committer | Chris Wilson <chris@chris-wilson.co.uk> | 2018-03-28 22:35:18 +0300 |
| commit | b6b0166d49f04ace13885a7ef42cb4a63ecf1f02 (patch) | |
| tree | 89800ace671bf6cde6173d0857d9f100bd9c2d26 /drivers/gpu/drm/i915/intel_guc.h | |
| parent | 6c77a2b05841a4082f746bf58345209df57175c9 (diff) | |
| download | linux-b6b0166d49f04ace13885a7ef42cb4a63ecf1f02.tar.xz | |
drm/i915/guc: Handle default action received over CT
When running on platform with CTB based GuC communication enabled,
GuC to Host event data will be delivered as CT request message.
However, content of the data[1] of this CT message follows format
of the scratch register used in MMIO based communication, so some
code reuse is still possible.
v2: filter disabled messages (Daniele)
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Oscar Mateo <oscar.mateo@intel.com>
Reviewed-by: Michel Thierry <michel.thierry@intel.com> #1
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Acked-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20180327214124.70680-1-michal.wajdeczko@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_guc.h')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_guc.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h index 6dc109ab61bc..f1265e122d30 100644 --- a/drivers/gpu/drm/i915/intel_guc.h +++ b/drivers/gpu/drm/i915/intel_guc.h @@ -163,6 +163,7 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len, void intel_guc_to_host_event_handler(struct intel_guc *guc); void intel_guc_to_host_event_handler_nop(struct intel_guc *guc); void intel_guc_to_host_event_handler_mmio(struct intel_guc *guc); +void intel_guc_to_host_process_recv_msg(struct intel_guc *guc, u32 msg); int intel_guc_sample_forcewake(struct intel_guc *guc); int intel_guc_auth_huc(struct intel_guc *guc, u32 rsa_offset); int intel_guc_suspend(struct intel_guc *guc); |