diff options
| author | Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> | 2018-03-14 21:26:53 +0300 |
|---|---|---|
| committer | Chris Wilson <chris@chris-wilson.co.uk> | 2018-03-15 11:46:06 +0300 |
| commit | fa6f071d54fb3658c7012634b8e4035c8d3a25bc (patch) | |
| tree | fe473a7450542c9fef82a9f2de321c32f9a683ae /drivers/gpu/drm/i915/intel_engine_cs.c | |
| parent | 210060edc216ebd6330ee4fded5a01547d938642 (diff) | |
| download | linux-fa6f071d54fb3658c7012634b8e4035c8d3a25bc.tar.xz | |
drm/i915: move gen8 irq shifts to intel_lrc.c
The only usage outside the intel_lrc.c file is in the ringbuffer
init, but the irq mask calculated there is then overwritten for
all engines that have a non-zero shift, so we can drop it.
This change is not aimed at code saving but at removing from
intel_engines information that does not apply to all gens that have
the engine. When checking without the temporary WARN_ON, code size
is basically unchanged.
v2: make the irq_shifts array static const
v3: rebase, move irq_shifts array to logical_ring_default_irqs
v4: move array inside the if and use u8 for it (Chris)
Suggested-by: Michel Thierry <michel.thierry@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20180314182653.26981-4-daniele.ceraolospurio@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_engine_cs.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_engine_cs.c | 10 |
1 files changed, 0 insertions, 10 deletions
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c index 8fda81126fbc..337dfa56a738 100644 --- a/drivers/gpu/drm/i915/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/intel_engine_cs.c @@ -92,7 +92,6 @@ struct engine_info { u32 gen : 8; u32 base : 24; } mmio_bases[MAX_MMIO_BASES]; - unsigned irq_shift; }; static const struct engine_info intel_engines[] = { @@ -104,7 +103,6 @@ static const struct engine_info intel_engines[] = { .mmio_bases = { { .gen = 1, .base = RENDER_RING_BASE } }, - .irq_shift = GEN8_RCS_IRQ_SHIFT, }, [BCS] = { .hw_id = BCS_HW, @@ -114,7 +112,6 @@ static const struct engine_info intel_engines[] = { .mmio_bases = { { .gen = 6, .base = BLT_RING_BASE } }, - .irq_shift = GEN8_BCS_IRQ_SHIFT, }, [VCS] = { .hw_id = VCS_HW, @@ -126,7 +123,6 @@ static const struct engine_info intel_engines[] = { { .gen = 6, .base = GEN6_BSD_RING_BASE }, { .gen = 4, .base = BSD_RING_BASE } }, - .irq_shift = GEN8_VCS1_IRQ_SHIFT, }, [VCS2] = { .hw_id = VCS2_HW, @@ -137,7 +133,6 @@ static const struct engine_info intel_engines[] = { { .gen = 11, .base = GEN11_BSD2_RING_BASE }, { .gen = 8, .base = GEN8_BSD2_RING_BASE } }, - .irq_shift = GEN8_VCS2_IRQ_SHIFT, }, [VCS3] = { .hw_id = VCS3_HW, @@ -147,7 +142,6 @@ static const struct engine_info intel_engines[] = { .mmio_bases = { { .gen = 11, .base = GEN11_BSD3_RING_BASE } }, - .irq_shift = 0, /* not used */ }, [VCS4] = { .hw_id = VCS4_HW, @@ -157,7 +151,6 @@ static const struct engine_info intel_engines[] = { .mmio_bases = { { .gen = 11, .base = GEN11_BSD4_RING_BASE } }, - .irq_shift = 0, /* not used */ }, [VECS] = { .hw_id = VECS_HW, @@ -168,7 +161,6 @@ static const struct engine_info intel_engines[] = { { .gen = 11, .base = GEN11_VEBOX_RING_BASE }, { .gen = 7, .base = VEBOX_RING_BASE } }, - .irq_shift = GEN8_VECS_IRQ_SHIFT, }, [VECS2] = { .hw_id = VECS2_HW, @@ -178,7 +170,6 @@ static const struct engine_info intel_engines[] = { .mmio_bases = { { .gen = 11, .base = GEN11_VEBOX2_RING_BASE } }, - .irq_shift = 0, /* not used */ }, }; @@ -301,7 +292,6 @@ intel_engine_setup(struct drm_i915_private *dev_priv, __sprint_engine_name(engine->name, info); engine->hw_id = engine->guc_id = info->hw_id; engine->mmio_base = __engine_mmio_base(dev_priv, info->mmio_bases); - engine->irq_shift = info->irq_shift; engine->class = info->class; engine->instance = info->instance; |