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| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2017-10-27 16:43:48 +0300 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2017-10-27 22:14:37 +0300 |
| commit | 5161d058dff4d53c78a046350d64beff54e9a9f7 (patch) | |
| tree | c07321569a956dcbff1f64944a72cfa0f2c03b8e /drivers/gpu/drm/i915/intel_ddi.c | |
| parent | 742745f1ee4f5a36e5cc5e8b360b519df45efa89 (diff) | |
| download | linux-5161d058dff4d53c78a046350d64beff54e9a9f7.tar.xz | |
drm/i915: Fix BXT lane latency optimal setting with MST
Call the DDI .pre_pll_enable() hook from the MST code so that BXT gets
the correct lane latency optimal setting applied. And we obviously need
to compute the correct value, and read it out to keep the state checker
happy.
While at it drop the useless 'encoder' parameter to
bxt_ddi_phy_calc_lane_lat_optim_mask()
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171027134348.31190-1-ville.syrjala@linux.intel.com
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_ddi.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_ddi.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index c721775687e7..9c118e5305f7 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -2662,8 +2662,7 @@ static bool intel_ddi_compute_config(struct intel_encoder *encoder, if (IS_GEN9_LP(dev_priv) && ret) pipe_config->lane_lat_optim_mask = - bxt_ddi_phy_calc_lane_lat_optim_mask(encoder, - pipe_config->lane_count); + bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); intel_ddi_compute_min_voltage_level(dev_priv, pipe_config); |