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authorChris Wilson <chris@chris-wilson.co.uk>2010-08-09 17:50:53 +0400
committerChris Wilson <chris@chris-wilson.co.uk>2010-09-08 13:13:31 +0400
commit19c55da11660fea1a0f1ddbb33ecf38d4f728799 (patch)
tree357a2a5fe9c39873e77ec396dd58589624d250c8 /drivers/gpu/drm/i915/intel_crt.c
parent82d7c9e7da9fa11b8ed968c94a19c7732e11c1ad (diff)
downloadlinux-19c55da11660fea1a0f1ddbb33ecf38d4f728799.tar.xz
drm/i915/crt: Flush register prior to waiting for vblank.
If we don't flush the write then we can not be sure that the border colour will have taken effect by the time we try to read it back. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_crt.c')
-rw-r--r--drivers/gpu/drm/i915/intel_crt.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index c2982e48b61f..626279791b89 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -327,6 +327,7 @@ intel_crt_load_detect(struct drm_crtc *crtc, struct intel_encoder *intel_encoder
if (IS_I9XX(dev)) {
uint32_t pipeconf = I915_READ(pipeconf_reg);
I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER);
+ POSTING_READ(pipeconf_reg);
/* Wait for next Vblank to substitue
* border color for Color info */
intel_wait_for_vblank(dev, pipe);