diff options
| author | Animesh Manna <animesh.manna@intel.com> | 2021-08-27 13:38:43 +0300 |
|---|---|---|
| committer | Jani Nikula <jani.nikula@intel.com> | 2021-08-30 13:24:44 +0300 |
| commit | 45cbbe50ccb10452c9369c2e58f0fdee90abae0b (patch) | |
| tree | cb3297b52c423bbc078b999c64d94025b102aa1c /drivers/gpu/drm/i915/i915_reg.h | |
| parent | fa3217c4948700d0d4e85c5fad41fe27d663a507 (diff) | |
| download | linux-45cbbe50ccb10452c9369c2e58f0fdee90abae0b.tar.xz | |
drm/i915/dg2: UHBR tables added for pll programming
UHBR modes has higher link rate and added new values for programming
mpll of SNPS phy. No change in sequence, only the pll parameters
are different for UHBR modes.
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210827103843.527-1-jani.nikula@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index d5177c7655b3..26c9825e0b89 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2237,10 +2237,14 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define SNPS_PHY_MPLLB_DIV(phy) _MMIO_SNPS(phy, 0x168004) #define SNPS_PHY_MPLLB_FORCE_EN REG_BIT(31) +#define SNPS_PHY_MPLLB_DIV_CLK_EN REG_BIT(30) #define SNPS_PHY_MPLLB_DIV5_CLK_EN REG_BIT(29) #define SNPS_PHY_MPLLB_V2I REG_GENMASK(27, 26) #define SNPS_PHY_MPLLB_FREQ_VCO REG_GENMASK(25, 24) +#define SNPS_PHY_MPLLB_DIV_MULTIPLIER REG_GENMASK(23, 16) #define SNPS_PHY_MPLLB_PMIX_EN REG_BIT(10) +#define SNPS_PHY_MPLLB_DP2_MODE REG_BIT(9) +#define SNPS_PHY_MPLLB_WORD_DIV2_EN REG_BIT(8) #define SNPS_PHY_MPLLB_TX_CLK_DIV REG_GENMASK(7, 5) #define SNPS_PHY_MPLLB_FRACN1(phy) _MMIO_SNPS(phy, 0x168008) |