diff options
| author | Chris Wilson <chris@chris-wilson.co.uk> | 2017-12-01 14:30:30 +0300 |
|---|---|---|
| committer | Chris Wilson <chris@chris-wilson.co.uk> | 2017-12-01 18:20:02 +0300 |
| commit | fb6db0f5bf1d4d3a4af6242e287fa795221ec5b8 (patch) | |
| tree | d2b137ab6210bc5d35679e31d1f3d184f24f7f18 /drivers/gpu/drm/i915/i915_pmu.c | |
| parent | f7096d40eea84d32eb1e3b0f2b4407167aae9a83 (diff) | |
| download | linux-fb6db0f5bf1d4d3a4af6242e287fa795221ec5b8.tar.xz | |
drm/i915: Remove unsafe i915.enable_rc6
It has been many years since the last confirmed sighting (and fix) of an
RC6 related bug (usually a system hang). Remove the parameter to stop
users from setting dangerous values, as they often set it during triage
and end up disabling the entire runtime pm instead (the option is not a
fine scalpel!).
Furthermore, it allows users to set known dangerous values which were
intended for testing and not for production use. For testing, we can
always patch in the required setting without having to expose ourselves
to random abuse.
v2: Fixup NEEDS_WaRsDisableCoarsePowerGating fumble, and document the
lack of ilk support better.
v3: Clear intel_info->rc6p if we don't support rc6 itself.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171201113030.18360-1-chris@chris-wilson.co.uk
Diffstat (limited to 'drivers/gpu/drm/i915/i915_pmu.c')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_pmu.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c index e8e2faf4982f..55a8a1e29424 100644 --- a/drivers/gpu/drm/i915/i915_pmu.c +++ b/drivers/gpu/drm/i915/i915_pmu.c @@ -413,12 +413,12 @@ static u64 __i915_pmu_event_read(struct perf_event *event) IS_VALLEYVIEW(i915) ? VLV_GT_RENDER_RC6 : GEN6_GT_GFX_RC6); - if (HAS_RC6p(i915)) { + if (HAS_RC6p(i915)) val += intel_rc6_residency_ns(i915, GEN6_GT_GFX_RC6p); + if (HAS_RC6pp(i915)) val += intel_rc6_residency_ns(i915, GEN6_GT_GFX_RC6pp); - } intel_runtime_pm_put(i915); break; } |