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authorGustavo Sousa <gustavo.sousa@intel.com>2023-09-20 22:53:52 +0300
committerLucas De Marchi <lucas.demarchi@intel.com>2023-09-25 19:04:32 +0300
commit156adfa55f23620f5817e1cf93dd6f762c8890b4 (patch)
tree8d95182f7190fdb21180ebcb363d528b2fc0f4f3 /drivers/gpu/drm/i915/i915_irq.c
parent3447aea1b5e11e4e3734b8b6becde038438d85a2 (diff)
downloadlinux-156adfa55f23620f5817e1cf93dd6f762c8890b4.tar.xz
drm/i915/irq: Clear GFX_MSTR_IRQ as part of IRQ reset
Starting with Xe_LP+, GFX_MSTR_IRQ contains status bits that have W1C behavior. If we do not properly reset them, we would miss delivery of interrupts if a pending bit is set when enabling IRQs. As an example, the display part of our probe routine contains paths where we wait for vblank interrupts. If a display interrupt was already pending when enabling IRQs, we would time out waiting for the vblank. Avoid the potential issue by clearing GFX_MSTR_IRQ as part of the IRQ reset. v2: - Move logic from gen11_gt_irq_reset() to dg1_irq_reset(). (Matt) BSpec: 50875, 54028 Cc: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230920195351.59421-2-gustavo.sousa@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/i915_irq.c')
-rw-r--r--drivers/gpu/drm/i915/i915_irq.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 1bfcfbe6e30b..8130f043693b 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -751,6 +751,8 @@ static void dg1_irq_reset(struct drm_i915_private *dev_priv)
GEN3_IRQ_RESET(uncore, GEN11_GU_MISC_);
GEN3_IRQ_RESET(uncore, GEN8_PCU_);
+
+ intel_uncore_write(uncore, GEN11_GFX_MSTR_IRQ, ~0);
}
static void cherryview_irq_reset(struct drm_i915_private *dev_priv)