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| author | Ramalingam C <ramalingam.c@intel.com> | 2016-04-07 12:06:07 +0300 |
|---|---|---|
| committer | Jani Nikula <jani.nikula@intel.com> | 2016-04-07 16:46:09 +0300 |
| commit | 6f0e7535e7e122d927081423f80ff2a7d21e0a3f (patch) | |
| tree | 7c40e14f260db537157778c64ef0bfbd6a3b7a31 /drivers/gpu/drm/i915/i915_gpu_error.c | |
| parent | 43367ec962095b76d36453b659defd9ee8d41e46 (diff) | |
| download | linux-6f0e7535e7e122d927081423f80ff2a7d21e0a3f.tar.xz | |
drm/i915/BXT: Get pipe conf from the port registers
At BXT DSI, PIPE registers are inactive. So we can't get the
PIPE's mode parameters from them. The possible option is
retriving them from the PORT registers.
The required changes are added for BXT in intel_dsi_get_config
(encoder->get_config).
v2: Addressed the Jani's comments
-removed the redundant call to encoder->get_config
-read bpp from port register
-removed retrival of src_size from encoder->get_config
v3: pipe_config->pipe_bpp is fixed
Jani's review comments addressed:
Few horizontal timing parameters dropped from the patch to make
progress, as there seems to be some disagreement on
best/feasible/possible options.
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Previously Reviewed at: https://lists.freedesktop.org/archives/intel-gfx/2016-April/091737.html
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1460019967-26501-2-git-send-email-ramalingam.c@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/i915_gpu_error.c')
0 files changed, 0 insertions, 0 deletions