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| author | Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> | 2021-02-23 00:30:06 +0300 |
|---|---|---|
| committer | José Roberto de Souza <jose.souza@intel.com> | 2021-02-23 19:00:23 +0300 |
| commit | 62c211bb9e1bee0083d8061ce0012f538ac754c3 (patch) | |
| tree | 3298cbe11c6327054ec388e7f0b21a1fc047aaf6 /drivers/gpu/drm/i915/gvt | |
| parent | 63e654f65d7cf588813c5b75beafe2d3114719b0 (diff) | |
| download | linux-62c211bb9e1bee0083d8061ce0012f538ac754c3.tar.xz | |
drm/i915/display: Do not allow DC3CO if PSR SF is enabled
Even though GEN12+ HW supports PSR + DC3CO, DMC's HW DC3CO exit mechanism
has an issue with using of Selective Fecth and PSR2 manual tracking.
And as some GEN12+ platforms (RKL, ADL-S) don't support PSR2 HW tracking,
Selective Fetch will be enabled by default on that platforms.
Therefore if the system enables PSR Selective Fetch / PSR manual tracking,
it does not allow DC3CO dc state, in that case.
When this DC3CO exit issue is addressed while PSR Selective Fetch is
enabled, this restriction should be removed.
v2: Address Jose's review comment.
- Fix typo
- Move check routine of DC3CO ability to
tgl_dc3co_exitline_compute_config()
v3: Change the check routine of enablement of psr2 sel fetch. (Jose)
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Anshuman Gupta <anshuman.gupta@intel.com>
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210222213006.1609085-1-gwan-gyeong.mun@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/gvt')
0 files changed, 0 insertions, 0 deletions