diff options
| author | Vandita Kulkarni <vandita.kulkarni@intel.com> | 2021-05-19 03:06:10 +0300 |
|---|---|---|
| committer | Lucas De Marchi <lucas.demarchi@intel.com> | 2021-05-20 09:59:12 +0300 |
| commit | c33ebdb717e9ffa0e5cae3f75c5f5795102bdc3b (patch) | |
| tree | d8abe4cb0a194ba12ffc1330b2f13df0baf3cf7f /drivers/gpu/drm/i915/display/intel_vdsc.c | |
| parent | db514cac08fd4861a3b221bed5f21b441a1242c3 (diff) | |
| download | linux-c33ebdb717e9ffa0e5cae3f75c5f5795102bdc3b.tar.xz | |
drm/i915/xelpd: Add rc_qp_table for rcparams calculation
Add the qp table for 444 formats, for 8bpc, 10bpc and 12bpc, as given by
the VESA C model for DSC 1.1
v2:
- Add include guard to header (Jani)
- Move the big tables to a .c file (Chris, Jani, Lucas)
v3:
- Make tables 'static const' and add lookup functions to index into
them. (Jani)
v3.1:
- Include missing .h file.
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210519000625.3184321-3-lucas.demarchi@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_vdsc.c')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_vdsc.c | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c index 02e86d2be395..19cd9531c115 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.c +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c @@ -11,6 +11,7 @@ #include "intel_display_types.h" #include "intel_dsi.h" #include "intel_vdsc.h" +#include "intel_qp_tables.h" enum ROW_INDEX_BPP { ROW_INDEX_6BPP = 0, @@ -384,7 +385,7 @@ calculate_rc_params(struct rc_parameters *rc, int ofs_und12[] = { 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12 }; int ofs_und15[] = { 10, 8, 6, 4, 2, 0, -2, -4, -6, -8, -10, -10, -12, -12, -12 }; int qp_bpc_modifier = (bpc - 8) * 2; - u32 res, buf_i; + u32 res, buf_i, bpp_i; if (vdsc_cfg->slice_height >= 8) rc->first_line_bpg_offset = @@ -411,7 +412,14 @@ calculate_rc_params(struct rc_parameters *rc, rc->rc_quant_incr_limit0 = 11 + qp_bpc_modifier; rc->rc_quant_incr_limit1 = 11 + qp_bpc_modifier; + bpp_i = (2 * (bpp - 6)); for (buf_i = 0; buf_i < DSC_NUM_BUF_RANGES; buf_i++) { + /* Read range_minqp and range_max_qp from qp tables */ + rc->rc_range_params[buf_i].range_min_qp = + intel_lookup_range_min_qp(bpc, buf_i, bpp_i); + rc->rc_range_params[buf_i].range_max_qp = + intel_lookup_range_max_qp(bpc, buf_i, bpp_i); + /* Calculate range_bgp_offset */ if (bpp <= 6) { rc->rc_range_params[buf_i].range_bpg_offset = ofs_und6[buf_i]; |