diff options
| author | Imre Deak <imre.deak@intel.com> | 2025-08-05 10:36:48 +0300 |
|---|---|---|
| committer | Imre Deak <imre.deak@intel.com> | 2025-08-13 15:02:36 +0300 |
| commit | 45d424856a074ea58c5a853e11bd0388a56a6951 (patch) | |
| tree | 34783053f7b708da68134d7dfcbd8d8a14c1347a /drivers/gpu/drm/i915/display/intel_tc.c | |
| parent | aaf01f66e0ee688f0df7eb941914c78fdecf1edd (diff) | |
| download | linux-45d424856a074ea58c5a853e11bd0388a56a6951.tar.xz | |
drm/i915/tc: Move getting the power domain before reading DFLEX registers
Move getting the required display power domain right before reading the
PORT_TX_DFLEXDPSP and PORT_TX_DFLEXPA1 registers, similarly to how this
is done while reading the other TCSS_DDI_STATUS PHY register.
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Link: https://lore.kernel.org/r/20250805073700.642107-8-imre.deak@intel.com
Signed-off-by: Imre Deak <imre.deak@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_tc.c')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_tc.c | 18 |
1 files changed, 8 insertions, 10 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c index f00fb6fc94d8..f311d403eef2 100644 --- a/drivers/gpu/drm/i915/display/intel_tc.c +++ b/drivers/gpu/drm/i915/display/intel_tc.c @@ -269,9 +269,11 @@ static u32 intel_tc_port_get_lane_mask(struct intel_digital_port *dig_port) { struct intel_display *display = to_intel_display(dig_port); struct intel_tc_port *tc = to_tc_port(dig_port); + intel_wakeref_t wakeref; u32 lane_mask; - lane_mask = intel_de_read(display, PORT_TX_DFLEXDPSP(tc->phy_fia)); + with_intel_display_power(display, POWER_DOMAIN_DISPLAY_CORE, wakeref) + lane_mask = intel_de_read(display, PORT_TX_DFLEXDPSP(tc->phy_fia)); drm_WARN_ON(display->drm, lane_mask == 0xffffffff); assert_tc_cold_blocked(tc); @@ -284,9 +286,11 @@ u32 intel_tc_port_get_pin_assignment_mask(struct intel_digital_port *dig_port) { struct intel_display *display = to_intel_display(dig_port); struct intel_tc_port *tc = to_tc_port(dig_port); + intel_wakeref_t wakeref; u32 pin_mask; - pin_mask = intel_de_read(display, PORT_TX_DFLEXPA1(tc->phy_fia)); + with_intel_display_power(display, POWER_DOMAIN_DISPLAY_CORE, wakeref) + pin_mask = intel_de_read(display, PORT_TX_DFLEXPA1(tc->phy_fia)); drm_WARN_ON(display->drm, pin_mask == 0xffffffff); assert_tc_cold_blocked(tc); @@ -324,12 +328,9 @@ static int lnl_tc_port_get_max_lane_count(struct intel_digital_port *dig_port) static int mtl_tc_port_get_max_lane_count(struct intel_digital_port *dig_port) { - struct intel_display *display = to_intel_display(dig_port); - intel_wakeref_t wakeref; u32 pin_mask; - with_intel_display_power(display, POWER_DOMAIN_DISPLAY_CORE, wakeref) - pin_mask = intel_tc_port_get_pin_assignment_mask(dig_port); + pin_mask = intel_tc_port_get_pin_assignment_mask(dig_port); switch (pin_mask) { default: @@ -345,12 +346,9 @@ static int mtl_tc_port_get_max_lane_count(struct intel_digital_port *dig_port) static int intel_tc_port_get_max_lane_count(struct intel_digital_port *dig_port) { - struct intel_display *display = to_intel_display(dig_port); - intel_wakeref_t wakeref; u32 lane_mask = 0; - with_intel_display_power(display, POWER_DOMAIN_DISPLAY_CORE, wakeref) - lane_mask = intel_tc_port_get_lane_mask(dig_port); + lane_mask = intel_tc_port_get_lane_mask(dig_port); switch (lane_mask) { default: |