Merge tag 'drm-fixes-2023-03-17' of git://anongit.freedesktop.org/drm/drm

Pull drm fixes from Dave Airlie:
 "Seems like a pretty regular rc3, i915 and amdgpu with the usual
  selection of fixes, then a scattering of fixes across misc drivers and
  other areas:

  accel:
   - build fix for accel

  edid:
   - fix info leak in edid

  ttm:
   - fix NULL ptr deref
   - reference counting fix

  i915:
   - Fix hwmon PL1 power limit enabling
   - Fix audio ELD handling for DP MST
   - Fix PSR io and wake line calculations
   - Fix DG2 HDMI modes with 267.30 and 319.89 MHz pixel clocks
   - Fix SSEU subslice out-of-bounds access
   - Fix misuse of non-idle barriers as fence trackers

  amdgpu:
   - SMU 13 update
   - RDNA2 suspend/resume fix when overclocking is enabled
   - SRIOV VCN fixes
   - HDCP suspend/resume fix
   - Fix drm polling splat regression
   - Fix dirty rectangle tracking for PSR
   - Fix vangogh regression on certain BIOSes
   - Misc display fixes
   - Suspend/resume IOMMU regression fix

  amdkfd:
   - Fix BO offset for multi-VMA page migration
   - Fix a possible double free
   - Fix potential use after free
   - Fix process cleanup on module exit

  bridge:
   - fix returned array size name documentation

  fbdev:
   - ref-counting fix for fbdev deferred I/O

  virtio:
   - dma sync fix

  shmem-helper:
   - error path fix

  msm:
   - shrinker blocking fix

  panfrost:
   - shrinker rpm fix

  chipsfb:
   - fix error code

  meson:
   - fix 1px pink line
   - fix regulator interaction

  sun4i:
   - fix missing component unbind"

* tag 'drm-fixes-2023-03-17' of git://anongit.freedesktop.org/drm/drm: (38 commits)
  drm/ttm: drop extra ttm_bo_put in ttm_bo_cleanup_refs
  drm/amdgpu: Don't resume IOMMU after incomplete init
  drm/amdkfd: Fixed kfd_process cleanup on module exit.
  drm/amd/display: disconnect MPCC only on OTG change
  drm/amd/display: Fix DP MST sinks removal issue
  drm/amd/display: Do not set DRR on pipe Commit
  drm/amd/display: Remove OTG DIV register write for Virtual signals.
  drm/meson: dw-hdmi: Fix devm_regulator_*get_enable*() conversion again
  drm/bridge: Fix returned array size name for atomic_get_input_bus_fmts kdoc
  drm/amdgpu/vcn: Disable indirect SRAM on Vangogh broken BIOSes
  drm/amdgpu/nv: fix codec array for SR_IOV
  drm/amd/display: Write to correct dirty_rect
  drm/amdgpu: move poll enabled/disable into non DC path
  drm/amd/display: Fix HDCP failing to enable after suspend
  drm/amdkfd: fix potential kgd_mem UAFs
  drm/amdgpu/vcn: custom video info caps for sriov
  drm/amd/pm: Fix sienna cichlid incorrect OD volage after resume
  drm/amd/pm: bump SMU 13.0.4 driver_if header version
  drm/amdkfd: fix a potential double free in pqm_create_queue
  drm/amdkfd: Get prange->offset after svm_range_vram_node_new
  ...

1 files changed, 61 insertions, 17 deletions

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 7a72e15e6836..9f1a0bebae24 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -542,6 +542,14 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
 	val |= EDP_PSR2_FRAME_BEFORE_SU(max_t(u8, intel_dp->psr.sink_sync_latency + 1, 2));
 	val |= intel_psr2_get_tp_time(intel_dp);
 
+	if (DISPLAY_VER(dev_priv) >= 12) {
+		if (intel_dp->psr.io_wake_lines < 9 &&
+		    intel_dp->psr.fast_wake_lines < 9)
+			val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_2;
+		else
+			val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_3;
+	}
+
 	/* Wa_22012278275:adl-p */
 	if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_E0)) {
 		static const u8 map[] = {
@@ -558,31 +566,21 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
 		 * Still using the default IO_BUFFER_WAKE and FAST_WAKE, see
 		 * comments bellow for more information
 		 */
-		u32 tmp, lines = 7;
-
-		val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_2;
+		u32 tmp;
 
-		tmp = map[lines - TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES];
+		tmp = map[intel_dp->psr.io_wake_lines - TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES];
 		tmp = tmp << TGL_EDP_PSR2_IO_BUFFER_WAKE_SHIFT;
 		val |= tmp;
 
-		tmp = map[lines - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES];
+		tmp = map[intel_dp->psr.fast_wake_lines - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES];
 		tmp = tmp << TGL_EDP_PSR2_FAST_WAKE_MIN_SHIFT;
 		val |= tmp;
 	} else if (DISPLAY_VER(dev_priv) >= 12) {
-		/*
-		 * TODO: 7 lines of IO_BUFFER_WAKE and FAST_WAKE are default
-		 * values from BSpec. In order to setting an optimal power
-		 * consumption, lower than 4k resolution mode needs to decrease
-		 * IO_BUFFER_WAKE and FAST_WAKE. And higher than 4K resolution
-		 * mode needs to increase IO_BUFFER_WAKE and FAST_WAKE.
-		 */
-		val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_2;
-		val |= TGL_EDP_PSR2_IO_BUFFER_WAKE(7);
-		val |= TGL_EDP_PSR2_FAST_WAKE(7);
+		val |= TGL_EDP_PSR2_IO_BUFFER_WAKE(intel_dp->psr.io_wake_lines);
+		val |= TGL_EDP_PSR2_FAST_WAKE(intel_dp->psr.fast_wake_lines);
 	} else if (DISPLAY_VER(dev_priv) >= 9) {
-		val |= EDP_PSR2_IO_BUFFER_WAKE(7);
-		val |= EDP_PSR2_FAST_WAKE(7);
+		val |= EDP_PSR2_IO_BUFFER_WAKE(intel_dp->psr.io_wake_lines);
+		val |= EDP_PSR2_FAST_WAKE(intel_dp->psr.fast_wake_lines);
 	}
 
 	if (intel_dp->psr.req_psr2_sdp_prior_scanline)
@@ -842,6 +840,46 @@ static bool _compute_psr2_sdp_prior_scanline_indication(struct intel_dp *intel_d
 	return true;
 }
 
+static bool _compute_psr2_wake_times(struct intel_dp *intel_dp,
+				     struct intel_crtc_state *crtc_state)
+{
+	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+	int io_wake_lines, io_wake_time, fast_wake_lines, fast_wake_time;
+	u8 max_wake_lines;
+
+	if (DISPLAY_VER(i915) >= 12) {
+		io_wake_time = 42;
+		/*
+		 * According to Bspec it's 42us, but based on testing
+		 * it is not enough -> use 45 us.
+		 */
+		fast_wake_time = 45;
+		max_wake_lines = 12;
+	} else {
+		io_wake_time = 50;
+		fast_wake_time = 32;
+		max_wake_lines = 8;
+	}
+
+	io_wake_lines = intel_usecs_to_scanlines(
+		&crtc_state->uapi.adjusted_mode, io_wake_time);
+	fast_wake_lines = intel_usecs_to_scanlines(
+		&crtc_state->uapi.adjusted_mode, fast_wake_time);
+
+	if (io_wake_lines > max_wake_lines ||
+	    fast_wake_lines > max_wake_lines)
+		return false;
+
+	if (i915->params.psr_safest_params)
+		io_wake_lines = fast_wake_lines = max_wake_lines;
+
+	/* According to Bspec lower limit should be set as 7 lines. */
+	intel_dp->psr.io_wake_lines = max(io_wake_lines, 7);
+	intel_dp->psr.fast_wake_lines = max(fast_wake_lines, 7);
+
+	return true;
+}
+
 static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
 				    struct intel_crtc_state *crtc_state)
 {
@@ -936,6 +974,12 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
 		return false;
 	}
 
+	if (!_compute_psr2_wake_times(intel_dp, crtc_state)) {
+		drm_dbg_kms(&dev_priv->drm,
+			    "PSR2 not enabled, Unable to use long enough wake times\n");
+		return false;
+	}
+
 	if (HAS_PSR2_SEL_FETCH(dev_priv)) {
 		if (!intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state) &&
 		    !HAS_PSR_HW_TRACKING(dev_priv)) {