diff options
| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2025-02-13 18:02:15 +0300 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2025-02-15 22:04:06 +0300 |
| commit | 2be189c9e82d0e522a22f7c31fa5a217e5ec0a85 (patch) | |
| tree | 9eab6068aa05d117457d69e9fb475820807d9c37 /drivers/gpu/drm/i915/display/intel_dpio_phy.c | |
| parent | 7105bf946fc308d2cefd54e0fcaa748840d9a2d9 (diff) | |
| download | linux-2be189c9e82d0e522a22f7c31fa5a217e5ec0a85.tar.xz | |
drm/i915: Relocate vlv_wait_port_ready()
While vlv_wait_port_ready() doens't directly talk to the VLV/CHV
DPIO PHY, the signals it's looking for do come from the PHY. So
it seems appropriate to relocate it into intel_dpio_phy.c.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250213150220.13580-8-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_dpio_phy.c')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_dpio_phy.c | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c b/drivers/gpu/drm/i915/display/intel_dpio_phy.c index 5f88702818d3..968b795206b3 100644 --- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c +++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c @@ -1156,3 +1156,37 @@ void vlv_phy_reset_lanes(struct intel_encoder *encoder, vlv_dpio_write(dev_priv, phy, VLV_PCS_DW1_GRP(ch), 0x00e00060); vlv_dpio_put(dev_priv); } + +void vlv_wait_port_ready(struct intel_display *display, + struct intel_digital_port *dig_port, + unsigned int expected_mask) +{ + u32 port_mask; + i915_reg_t dpll_reg; + + switch (dig_port->base.port) { + default: + MISSING_CASE(dig_port->base.port); + fallthrough; + case PORT_B: + port_mask = DPLL_PORTB_READY_MASK; + dpll_reg = DPLL(display, 0); + break; + case PORT_C: + port_mask = DPLL_PORTC_READY_MASK; + dpll_reg = DPLL(display, 0); + expected_mask <<= 4; + break; + case PORT_D: + port_mask = DPLL_PORTD_READY_MASK; + dpll_reg = DPIO_PHY_STATUS; + break; + } + + if (intel_de_wait(display, dpll_reg, port_mask, expected_mask, 1000)) + drm_WARN(display->drm, 1, + "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n", + dig_port->base.base.base.id, dig_port->base.base.name, + intel_de_read(display, dpll_reg) & port_mask, + expected_mask); +} |