diff options
| author | Jani Nikula <jani.nikula@intel.com> | 2022-08-29 16:18:16 +0300 |
|---|---|---|
| committer | Jani Nikula <jani.nikula@intel.com> | 2022-08-31 15:19:58 +0300 |
| commit | e3e8148f43fb6d4347211ea2160e7de9b8ddde81 (patch) | |
| tree | 1e90252e6bc19f68f2ebee2d8feaa04db7b0cd76 /drivers/gpu/drm/i915/display/intel_display_power_map.c | |
| parent | 80b3842f21f8af1bac5750105f557b29af854291 (diff) | |
| download | linux-e3e8148f43fb6d4347211ea2160e7de9b8ddde81.tar.xz | |
drm/i915: move and group power related members under display.power
Move display power related members under drm_i915_private display
sub-struct.
Arguably chv_phy_control and chv_phy_assert could be placed in a phy
substruct, but they are only used in the power code.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/57bfa82f6fe85a775f80c398b2a7dff77b9452b0.1661779055.git.jani.nikula@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_display_power_map.c')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_display_power_map.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c index 97b367f39f35..5ddd1b93751c 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power_map.c +++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c @@ -1388,7 +1388,7 @@ __set_power_wells(struct i915_power_domains *power_domains, { struct drm_i915_private *i915 = container_of(power_domains, struct drm_i915_private, - power_domains); + display.power.domains); u64 power_well_ids = 0; const struct i915_power_well_desc_list *desc_list; const struct i915_power_well_desc *desc; @@ -1447,7 +1447,7 @@ int intel_display_power_map_init(struct i915_power_domains *power_domains) { struct drm_i915_private *i915 = container_of(power_domains, struct drm_i915_private, - power_domains); + display.power.domains); /* * The enabling order will be from lower to higher indexed wells, * the disabling order is reversed. |