diff options
| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2024-05-10 18:23:29 +0300 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2024-05-15 14:11:24 +0300 |
| commit | 19be15dcc0f6bcb4be9109faf2d50771fc9a80e1 (patch) | |
| tree | e73ba8fd9a9ade7d2faeaeedaa7915ee9e9ea703 /drivers/gpu/drm/i915/display/intel_cursor.c | |
| parent | 09fc93141d4c6ba3f6e78ce3c995c9dedac4a37c (diff) | |
| download | linux-19be15dcc0f6bcb4be9109faf2d50771fc9a80e1.tar.xz | |
drm/i915: Handle SKL+ WM/DDB registers next to all other plane registers
Having the plane WM/DDB regitster write functions in skl_watermarks.c
is rather annoying when trying to implement DSB based plane updates.
Move them into the respective files that handle all other plane
register writes. Less places where I need to worry about the DSB
vs. MMIO decisions.
The downside is that we spread the wm struct details a bit further
afield. But if that becomes too annoying we can probably abstract
things a bit more with a few extra functions.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240510152329.24098-17-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_cursor.c')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_cursor.c | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c index d2b459634732..3ecab15d1431 100644 --- a/drivers/gpu/drm/i915/display/intel_cursor.c +++ b/drivers/gpu/drm/i915/display/intel_cursor.c @@ -24,6 +24,7 @@ #include "intel_psr.h" #include "intel_psr_regs.h" #include "intel_vblank.h" +#include "skl_universal_plane.h" #include "skl_watermark.h" #include "gem/i915_gem_object.h" @@ -556,6 +557,37 @@ static void i9xx_cursor_update_sel_fetch_arm(struct intel_plane *plane, } } +static void skl_write_cursor_wm(struct intel_plane *plane, + const struct intel_crtc_state *crtc_state) +{ + struct drm_i915_private *i915 = to_i915(plane->base.dev); + enum plane_id plane_id = plane->id; + enum pipe pipe = plane->pipe; + const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal; + const struct skl_ddb_entry *ddb = + &crtc_state->wm.skl.plane_ddb[plane_id]; + int level; + + for (level = 0; level < i915->display.wm.num_levels; level++) + intel_de_write_fw(i915, CUR_WM(pipe, level), + skl_plane_wm_reg_val(skl_plane_wm_level(pipe_wm, plane_id, level))); + + intel_de_write_fw(i915, CUR_WM_TRANS(pipe), + skl_plane_wm_reg_val(skl_plane_trans_wm(pipe_wm, plane_id))); + + if (HAS_HW_SAGV_WM(i915)) { + const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id]; + + intel_de_write_fw(i915, CUR_WM_SAGV(pipe), + skl_plane_wm_reg_val(&wm->sagv.wm0)); + intel_de_write_fw(i915, CUR_WM_SAGV_TRANS(pipe), + skl_plane_wm_reg_val(&wm->sagv.trans_wm)); + } + + intel_de_write_fw(i915, CUR_BUF_CFG(pipe), + skl_plane_ddb_reg_val(ddb)); +} + /* TODO: split into noarm+arm pair */ static void i9xx_cursor_update_arm(struct intel_plane *plane, const struct intel_crtc_state *crtc_state, |