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authorTobias Jakobi <tjakobi@math.uni-bielefeld.de>2017-03-10 17:21:54 +0300
committerInki Dae <inki.dae@samsung.com>2017-06-01 10:21:36 +0300
commit2a6e4cd53c498c6762d9fa69745b84ff99815905 (patch)
tree9937b9c8e0f21a2eefcb9062488629ca983a3b5e /drivers/gpu/drm/exynos/regs-mixer.h
parent2a39db01361ec378718648de90a6e817f891b8d4 (diff)
downloadlinux-2a6e4cd53c498c6762d9fa69745b84ff99815905.tar.xz
drm/exynos: mixer: document YCbCr magic numbers
The output stage of the mixer uses YCbCr for the internal computations, which is the reason that some registers take YCbCr related data as input. In particular this applies to MXR_BG_COLOR{0,1,2} and MXR_CM_COEFF_{Y,CB,CR}. Document the formatting of the data which we write to these registers. While at it, unify wording of comments in the register header. Reviewed-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Tobias Jakobi <tjakobi@math.uni-bielefeld.de> Signed-off-by: Inki Dae <inki.dae@samsung.com>
Diffstat (limited to 'drivers/gpu/drm/exynos/regs-mixer.h')
-rw-r--r--drivers/gpu/drm/exynos/regs-mixer.h7
1 files changed, 5 insertions, 2 deletions
diff --git a/drivers/gpu/drm/exynos/regs-mixer.h b/drivers/gpu/drm/exynos/regs-mixer.h
index 7f22df5bf707..c311f571bdf9 100644
--- a/drivers/gpu/drm/exynos/regs-mixer.h
+++ b/drivers/gpu/drm/exynos/regs-mixer.h
@@ -140,11 +140,11 @@
#define MXR_INT_EN_VSYNC (1 << 11)
#define MXR_INT_EN_ALL (0x0f << 8)
-/* bit for MXR_INT_STATUS */
+/* bits for MXR_INT_STATUS */
#define MXR_INT_CLEAR_VSYNC (1 << 11)
#define MXR_INT_STATUS_VSYNC (1 << 0)
-/* bit for MXR_LAYER_CFG */
+/* bits for MXR_LAYER_CFG */
#define MXR_LAYER_CFG_GRP1_VAL(x) MXR_MASK_VAL(x, 11, 8)
#define MXR_LAYER_CFG_GRP1_MASK MXR_LAYER_CFG_GRP1_VAL(~0)
#define MXR_LAYER_CFG_GRP0_VAL(x) MXR_MASK_VAL(x, 7, 4)
@@ -152,5 +152,8 @@
#define MXR_LAYER_CFG_VP_VAL(x) MXR_MASK_VAL(x, 3, 0)
#define MXR_LAYER_CFG_VP_MASK MXR_LAYER_CFG_VP_VAL(~0)
+/* bits for MXR_CM_COEFF_Y */
+#define MXR_CM_COEFF_RGB_FULL (1 << 30)
+
#endif /* SAMSUNG_REGS_MIXER_H */