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authorSung Lee <sung.lee@amd.com>2021-02-26 21:20:43 +0300
committerAlex Deucher <alexander.deucher@amd.com>2021-03-11 00:16:27 +0300
commitb0075d114c33580f5c9fa9cee8e13d06db41471b (patch)
treea9853359a5528b4e64d53eabca0f27958f99bf51 /drivers/gpu/drm/amd/display/dc
parent7afa0033d6f7fb8a84798ef99d1117661c4e696c (diff)
downloadlinux-b0075d114c33580f5c9fa9cee8e13d06db41471b.tar.xz
drm/amd/display: Revert dram_clock_change_latency for DCN2.1
[WHY & HOW] Using values provided by DF for latency may cause hangs in multi display configurations. Revert change to previous value. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Sung Lee <sung.lee@amd.com> Reviewed-by: Haonan Wang <Haonan.Wang2@amd.com> Acked-by: Eryk Brol <eryk.brol@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc')
-rw-r--r--drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
index 94ee2cab26b7..173488ab787a 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
@@ -296,7 +296,7 @@ struct _vcs_dpi_soc_bounding_box_st dcn2_1_soc = {
.num_banks = 8,
.num_chans = 4,
.vmm_page_size_bytes = 4096,
- .dram_clock_change_latency_us = 11.72,
+ .dram_clock_change_latency_us = 23.84,
.return_bus_width_bytes = 64,
.dispclk_dppclk_vco_speed_mhz = 3600,
.xfc_bus_transport_time_us = 4,