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| author | Martin Leung <martin.leung@amd.com> | 2019-07-09 22:15:17 +0300 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2019-08-15 18:54:14 +0300 |
| commit | 8a31820b12187c7e31c52e8a00075359d9efac52 (patch) | |
| tree | d27fc74b20cb7b04edf3287de1b6af4a423e0e06 /drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | |
| parent | 61e29b21cb2c6e87122015c8a0c4c3e26a7b4be4 (diff) | |
| download | linux-8a31820b12187c7e31c52e8a00075359d9efac52.tar.xz | |
drm/amd/display: Make init_hw and init_pipes generic for seamless boot
[Why]
For seamless boot the init_hw sequence must be split into
actual hardware vs pipes, in order to defer pipe initialization to set mode
and skip of pipe-destructive sequences
[How]
made dcn10_init_hw and dcn10_init_pipes generic for future dcns to inherit
deleted dcn20 specific versions. This is part 1 of a 2 partimplementation
of seamless boot
Signed-off-by: Martin Leung <martin.leung@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h index 28645e10f854..80de2febd7cb 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h @@ -78,6 +78,8 @@ struct stream_resource; struct dc_phy_addr_space_config; struct dc_virtual_addr_space_config; #endif +struct hubp; +struct dpp; struct hw_sequencer_funcs { @@ -280,6 +282,36 @@ struct hw_sequencer_funcs { void (*setup_vupdate_interrupt)(struct pipe_ctx *pipe_ctx); bool (*did_underflow_occur)(struct dc *dc, struct pipe_ctx *pipe_ctx); + void (*init_blank)(struct dc *dc, struct timing_generator *tg); + void (*disable_vga)(struct dce_hwseq *hws); + void (*bios_golden_init)(struct dc *dc); + void (*plane_atomic_power_down)(struct dc *dc, + struct dpp *dpp, + struct hubp *hubp); + + void (*plane_atomic_disable)( + struct dc *dc, struct pipe_ctx *pipe_ctx); + + void (*enable_power_gating_plane)( + struct dce_hwseq *hws, + bool enable); + + void (*dpp_pg_control)( + struct dce_hwseq *hws, + unsigned int dpp_inst, + bool power_on); + + void (*hubp_pg_control)( + struct dce_hwseq *hws, + unsigned int hubp_inst, + bool power_on); + + void (*dsc_pg_control)( + struct dce_hwseq *hws, + unsigned int dsc_inst, + bool power_on); + + #if defined(CONFIG_DRM_AMD_DC_DCN2_0) void (*update_odm)(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx); void (*program_all_writeback_pipes_in_tree)( |