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authorNicholas Kazlauskas <nicholas.kazlauskas@amd.com>2022-07-12 21:32:45 +0300
committerAlex Deucher <alexander.deucher@amd.com>2022-07-26 00:15:12 +0300
commita7cefb0b40dcfdafedc54a3ba659327d0336956d (patch)
treeb7ee4ac0e8ac6ae4d8b3cacfafcefb8c25d11554 /drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
parent319568d75f5f91cd4f362b26e65af2a4437c64bf (diff)
downloadlinux-a7cefb0b40dcfdafedc54a3ba659327d0336956d.tar.xz
drm/amd/display: Guard against zero memory channels
[Why] If BIOS doesn't specify number of memory channels then bandwidth validation will fail due to insufficient BW in DML. [How] If BIOS is setting zero channels then use the default in the table. If no entry is in the table and no BIOS value is specified then throw an ASSERT for future developers to look into. Reviewed-by: Michael Strauss <Michael.Strauss@amd.com> Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c')
-rw-r--r--drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c5
1 files changed, 4 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
index 450ebd838505..56ada096c89d 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
@@ -1916,8 +1916,11 @@ static void dcn314_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *b
dcn3_14_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator;
dcn3_14_ip.max_num_dpp = dc->res_pool->pipe_count;
- dcn3_14_soc.num_chans = bw_params->num_channels;
+ if (bw_params->num_channels > 0)
+ dcn3_14_soc.num_chans = bw_params->num_channels;
+
+ ASSERT(dcn3_14_soc.num_chans);
ASSERT(clk_table->num_entries);
/* Prepass to find max clocks independent of voltage level. */