diff options
| author | Alex Hung <alex.hung@amd.com> | 2024-06-08 07:09:53 +0300 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2024-07-01 23:06:53 +0300 |
| commit | bbd0d1c942cbac87404ed2bca0aa4f7907b8f47f (patch) | |
| tree | b5d6ff653f2dab7da511791b8ae020b9081dc842 /drivers/gpu/drm/amd/display/dc/dce | |
| parent | 95134e5852978a92d2290a3b1ee93189e75507ac (diff) | |
| download | linux-bbd0d1c942cbac87404ed2bca0aa4f7907b8f47f.tar.xz | |
drm/amd/display: Fix possible overflow in integer multiplication
[WHAT & HOW]
Integer multiplies integer may overflow in context that expects an
expression of unsigned/siged long long (64 bits). This can be fixed
by casting integer to unsigned/siged long long to force 64 bits results.
This fixes 26 OVERFLOW_BEFORE_WIDEN issues reported by Coverity.
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Jerry Zuo <jerry.zuo@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dce')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dce/dce_audio.c | 2 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c | 8 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.c | 2 |
3 files changed, 6 insertions, 6 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c index 12f3c35b3a34..c3deb4ab3992 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c @@ -353,7 +353,7 @@ static uint32_t calculate_required_audio_bw_in_symbols( /* DP spec recommends between 1.05 to 1.1 safety margin to prevent sample under-run */ struct fixed31_32 audio_sdp_margin = dc_fixpt_from_fraction(110, 100); struct fixed31_32 horizontal_line_freq_khz = dc_fixpt_from_fraction( - crtc_info->requested_pixel_clock_100Hz, crtc_info->h_total * 10); + crtc_info->requested_pixel_clock_100Hz, (long long)crtc_info->h_total * 10); struct fixed31_32 samples_per_line; struct fixed31_32 layouts_per_line; struct fixed31_32 symbols_per_sdp_max_layout; diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c index 042a4187fff4..b700608e4240 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c @@ -217,7 +217,7 @@ static bool calc_fb_divider_checking_tolerance( actual_calc_clk_100hz = (uint64_t)feedback_divider * calc_pll_cs->fract_fb_divider_factor + fract_feedback_divider; - actual_calc_clk_100hz *= calc_pll_cs->ref_freq_khz * 10; + actual_calc_clk_100hz *= (uint64_t)calc_pll_cs->ref_freq_khz * 10; actual_calc_clk_100hz = div_u64(actual_calc_clk_100hz, ref_divider * post_divider * @@ -680,7 +680,7 @@ static bool calculate_ss( * so have to divided by 100 * 100*/ ss_amount = dc_fixpt_mul( fb_div, dc_fixpt_from_fraction(ss_data->percentage, - 100 * ss_data->percentage_divider)); + 100 * (long long)ss_data->percentage_divider)); ds_data->feedback_amount = dc_fixpt_floor(ss_amount); ss_nslip_amount = dc_fixpt_sub(ss_amount, @@ -695,8 +695,8 @@ static bool calculate_ss( /* compute SS_STEP_SIZE_DSFRAC */ modulation_time = dc_fixpt_from_fraction( - pll_settings->reference_freq * 1000, - pll_settings->reference_divider * ss_data->modulation_freq_hz); + pll_settings->reference_freq * (uint64_t)1000, + pll_settings->reference_divider * (uint64_t)ss_data->modulation_freq_hz); if (ss_data->flags.CENTER_SPREAD) modulation_time = dc_fixpt_div_int(modulation_time, 4); diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.c b/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.c index 5bca67407c5b..de31fb1b6819 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.c @@ -218,7 +218,7 @@ static void dce_driver_set_backlight(struct panel_cntl *panel_cntl, * contain integer component, lower 16 bits contain fractional component * of active duty cycle e.g. 0x21BDC0 = 0xEFF0 * 0x24 */ - active_duty_cycle = backlight_pwm_u16_16 * masked_pwm_period; + active_duty_cycle = backlight_pwm_u16_16 * (uint64_t)masked_pwm_period; /* 1.3 Calculate 16 bit active duty cycle from integer and fractional * components shift by bitCount then mask 16 bits and add rounding bit |