diff options
| author | Hersen Wu <hersenxs.wu@amd.com> | 2017-06-09 18:32:06 +0300 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2017-09-27 01:08:00 +0300 |
| commit | 3f6d743598ef24002f0babd3aa06c7fe104b7dc5 (patch) | |
| tree | 7f11457b86df86d3139c10cc1efd8800119786bb /drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c | |
| parent | 7f5c22d1652327b64375e88b184b0df502c7bdc7 (diff) | |
| download | linux-3f6d743598ef24002f0babd3aa06c7fe104b7dc5.tar.xz | |
drm/amd/display: DAL3 RV get DPREFCLK SpreadspectrumInfo from smu_info
Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c | 29 |
1 files changed, 28 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c index 04cd70172cc7..84b0860190d7 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c @@ -246,6 +246,33 @@ static int dce_clocks_get_dp_ref_freq(struct display_clock *clk) return dp_ref_clk_khz; } +/* TODO: This is DCN DPREFCLK: it could be program by DENTIST by VBIOS + * or CLK0_CLK11 by SMU. For DCE120, it is wlays 600Mhz. Will re-visit + * clock implementation + */ +static int dce_clocks_get_dp_ref_freq_wrkaround(struct display_clock *clk) +{ + struct dce_disp_clk *clk_dce = TO_DCE_CLOCKS(clk); + int dp_ref_clk_khz = 600000; + + if (clk_dce->ss_on_dprefclk && clk_dce->dprefclk_ss_divider != 0) { + struct fixed32_32 ss_percentage = dal_fixed32_32_div_int( + dal_fixed32_32_from_fraction( + clk_dce->dprefclk_ss_percentage, + clk_dce->dprefclk_ss_divider), 200); + struct fixed32_32 adj_dp_ref_clk_khz; + + ss_percentage = dal_fixed32_32_sub(dal_fixed32_32_one, + ss_percentage); + adj_dp_ref_clk_khz = + dal_fixed32_32_mul_int( + ss_percentage, + dp_ref_clk_khz); + dp_ref_clk_khz = dal_fixed32_32_floor(adj_dp_ref_clk_khz); + } + + return dp_ref_clk_khz; +} static enum dm_pp_clocks_state dce_get_required_clocks_state( struct display_clock *clk, struct state_dependent_clocks *req_clocks) @@ -605,7 +632,7 @@ static bool dce_apply_clock_voltage_request( static const struct display_clock_funcs dce120_funcs = { - .get_dp_ref_clk_frequency = dce_clocks_get_dp_ref_freq, + .get_dp_ref_clk_frequency = dce_clocks_get_dp_ref_freq_wrkaround, .apply_clock_voltage_request = dce_apply_clock_voltage_request, .set_clock = dce112_set_clock }; |