drm/amd/display: Implement DSC MST fair share algorithm

[why]
The current policy will always enable DSC to 12 bpp
regardless of if the current bandwidth is enough for MST displays.
This logic is not optimal because user will get lower quality output
if DSC compression is enabled.
This change to is to implement a DSC MST bandwidth fair share
algorithm so we will dynamically decide if DSC is needed and what
quality (target bpp) is needed to fairly destribute the MST bandwidth
in one MST topology. This will allow user to see the most optimal
image quality with the given bandwidth.

[how]
We will start with lowest bandwidth possible and run a
Max-Min fairness algorithm to fairly distribute the available
bandwidth. If there is still remaining bandwidth, we will try to fit
the timing without DSC compression.

Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Acked-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

1 files changed, 2 insertions, 0 deletions

diff --git a/drivers/gpu/drm/amd/display/dc/dc_dsc.h b/drivers/gpu/drm/amd/display/dc/dc_dsc.h
index 2cba6bd7937a..ddaf7532bb59 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dsc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_dsc.h
@@ -38,6 +38,8 @@ bool dc_dsc_parse_dsc_dpcd(const uint8_t *dpcd_dsc_data,
 
 bool dc_dsc_compute_bandwidth_range(
 		const struct dc *dc,
+		const uint32_t min_kbps,
+		const uint32_t max_kbps,
 		const struct dsc_dec_dpcd_caps *dsc_sink_caps,
 		const struct dc_crtc_timing *timing,
 		struct dc_dsc_bw_range *range);