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authorSung Joon Kim <Sungjoon.Kim@amd.com>2024-08-16 01:45:19 +0300
committerAlex Deucher <alexander.deucher@amd.com>2024-08-21 05:14:13 +0300
commitf327189389785b26e49904a7d3ba0c96506a4586 (patch)
tree8c7eec4da1ac629784d35c569f717af2285fe991 /drivers/gpu/drm/amd/display/dc/dc.h
parent272e6aab14bbf98d7a06b2b1cd6308a02d4a10a1 (diff)
downloadlinux-f327189389785b26e49904a7d3ba0c96506a4586.tar.xz
drm/amd/display: Support UHBR10 link rate on eDP
[why] Supporting UHBR10 link rate on eDP leverages the existing DP2.0 code but need to add some small adjustments in code. [how] Acknowledge the given DPCD caps for UHBR10 link rate support and allow DP2.0 programming sequence and link training for eDP. Reviewed-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: Sung Joon Kim <Sungjoon.Kim@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dc.h')
-rw-r--r--drivers/gpu/drm/amd/display/dc/dc.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 6b036417a73a..3de311533571 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -1760,6 +1760,7 @@ struct dc_link {
bool dongle_mode_timing_override;
bool blank_stream_on_ocs_change;
bool read_dpcd204h_on_irq_hpd;
+ bool disable_assr_for_uhbr;
} wa_flags;
struct link_mst_stream_allocation_table mst_stream_alloc_table;