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authorLinus Torvalds <torvalds@linux-foundation.org>2025-03-21 07:29:58 +0300
committerLinus Torvalds <torvalds@linux-foundation.org>2025-03-21 07:29:58 +0300
commitb3ee1e4609512dfff642a96b34d7e5dfcdc92d05 (patch)
tree25d90358ef1946c490e8168bc67753fca2983e52 /drivers/gpu/drm/amd/amdgpu/vi.c
parenta7ea35b61e37149963d975814104302fe8d69862 (diff)
parent41e09ef6c26f0bd89f93691ef967fd621a38d759 (diff)
downloadlinux-b3ee1e4609512dfff642a96b34d7e5dfcdc92d05.tar.xz
Merge tag 'drm-fixes-2025-03-21' of https://gitlab.freedesktop.org/drm/kernel
Pull drm fixes from Dave Airlie: "Just the usual spread of a bunch for amdgpu, and small changes to others. scheduler: - fix fence reference leak xe: - Fix for an error if exporting a dma-buf multiple time amdgpu: - Fix video caps limits on several asics - SMU 14.x fixes - GC 12 fixes - eDP fixes - DMUB fix amdkfd: - GC 12 trap handler fix - GC 7/8 queue validation fix radeon: - VCE IB parsing fix v3d: - fix job error handling bugs qaic: - fix two integer overflows host1x: - fix NULL domain handling" * tag 'drm-fixes-2025-03-21' of https://gitlab.freedesktop.org/drm/kernel: (21 commits) drm/xe: Fix exporting xe buffers multiple times gpu: host1x: Do not assume that a NULL domain means no DMA IOMMU drm/amdgpu/pm: Handle SCLK offset correctly in overdrive for smu 14.0.2 drm/amd/display: Fix incorrect fw_state address in dmub_srv drm/amd/display: Use HW lock mgr for PSR1 when only one eDP drm/amd/display: Fix message for support_edp0_on_dp1 drm/amdkfd: Fix user queue validation on Gfx7/8 drm/amdgpu: Restore uncached behaviour on GFX12 drm/amdgpu/gfx12: correct cleanup of 'me' field with gfx_v12_0_me_fini() drm/amdkfd: Fix instruction hazard in gfx12 trap handler drm/amdgpu/pm: wire up hwmon fan speed for smu 14.0.2 drm/amd/pm: add unique_id for gfx12 drm/amdgpu: Remove JPEG from vega and carrizo video caps drm/amdgpu: Fix JPEG video caps max size for navi1x and raven drm/amdgpu: Fix MPEG2, MPEG4 and VC1 video caps max size drm/radeon: fix uninitialized size issue in radeon_vce_cs_parse() accel/qaic: Fix integer overflow in qaic_validate_req() accel/qaic: Fix possible data corruption in BOs > 2G drm/v3d: Set job pointer to NULL when the job's fence has an error drm/v3d: Don't run jobs that have errors flagged in its fence ...
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/vi.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/vi.c43
1 files changed, 18 insertions, 25 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index 06615f160331..0c9c4d8b7b71 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -167,16 +167,16 @@ static const struct amdgpu_video_codec_info tonga_video_codecs_decode_array[] =
{
{
.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2,
- .max_width = 4096,
- .max_height = 4096,
- .max_pixels_per_frame = 4096 * 4096,
+ .max_width = 1920,
+ .max_height = 1088,
+ .max_pixels_per_frame = 1920 * 1088,
.max_level = 3,
},
{
.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4,
- .max_width = 4096,
- .max_height = 4096,
- .max_pixels_per_frame = 4096 * 4096,
+ .max_width = 1920,
+ .max_height = 1088,
+ .max_pixels_per_frame = 1920 * 1088,
.max_level = 5,
},
{
@@ -188,9 +188,9 @@ static const struct amdgpu_video_codec_info tonga_video_codecs_decode_array[] =
},
{
.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1,
- .max_width = 4096,
- .max_height = 4096,
- .max_pixels_per_frame = 4096 * 4096,
+ .max_width = 1920,
+ .max_height = 1088,
+ .max_pixels_per_frame = 1920 * 1088,
.max_level = 4,
},
};
@@ -206,16 +206,16 @@ static const struct amdgpu_video_codec_info cz_video_codecs_decode_array[] =
{
{
.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2,
- .max_width = 4096,
- .max_height = 4096,
- .max_pixels_per_frame = 4096 * 4096,
+ .max_width = 1920,
+ .max_height = 1088,
+ .max_pixels_per_frame = 1920 * 1088,
.max_level = 3,
},
{
.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4,
- .max_width = 4096,
- .max_height = 4096,
- .max_pixels_per_frame = 4096 * 4096,
+ .max_width = 1920,
+ .max_height = 1088,
+ .max_pixels_per_frame = 1920 * 1088,
.max_level = 5,
},
{
@@ -227,9 +227,9 @@ static const struct amdgpu_video_codec_info cz_video_codecs_decode_array[] =
},
{
.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1,
- .max_width = 4096,
- .max_height = 4096,
- .max_pixels_per_frame = 4096 * 4096,
+ .max_width = 1920,
+ .max_height = 1088,
+ .max_pixels_per_frame = 1920 * 1088,
.max_level = 4,
},
{
@@ -239,13 +239,6 @@ static const struct amdgpu_video_codec_info cz_video_codecs_decode_array[] =
.max_pixels_per_frame = 4096 * 4096,
.max_level = 186,
},
- {
- .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG,
- .max_width = 4096,
- .max_height = 4096,
- .max_pixels_per_frame = 4096 * 4096,
- .max_level = 0,
- },
};
static const struct amdgpu_video_codecs cz_video_codecs_decode =