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| author | Alex Deucher <alexander.deucher@amd.com> | 2019-09-17 23:12:18 +0300 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2019-10-03 17:10:59 +0300 |
| commit | e8186eeccb84eb41a87c9e6ffad2c9e61f3e3636 (patch) | |
| tree | d8325d012844965bd6c5b07efdf87703a3794493 /drivers/gpu/drm/amd/amdgpu/psp_v10_0.c | |
| parent | 5222d26146029bffa6d94d14315529cddaac96cf (diff) | |
| download | linux-e8186eeccb84eb41a87c9e6ffad2c9e61f3e3636.tar.xz | |
drm/amdgpu/psp: flush HDP write fifo after submitting cmds to the psp
We need to make sure the fifo is flushed before we ask the psp to
process the commands.
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/psp_v10_0.c')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/psp_v10_0.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c index 6ee33f368e21..b96484a72535 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c @@ -266,6 +266,7 @@ static int psp_v10_0_cmd_submit(struct psp_context *psp, write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); write_frame->fence_value = index; + amdgpu_asic_flush_hdp(adev, NULL); /* Update the write Pointer in DWORDs */ psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; |