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author | Andre Przywara <andre.przywara@arm.com> | 2025-03-07 03:26:27 +0300 |
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committer | Chen-Yu Tsai <wens@csie.org> | 2025-03-12 06:58:11 +0300 |
commit | a36cc6cd0feb7ea656a1a33db0e6347149f50fed (patch) | |
tree | 45a6b3eb75388c76034322592e426d4718202c5c /drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | |
parent | f3dabb29f0ca44f2053c0c3943ca6f47b248d348 (diff) | |
download | linux-a36cc6cd0feb7ea656a1a33db0e6347149f50fed.tar.xz |
clk: sunxi-ng: a523: add reset lines
Allwinner SoCs do not contain a separate reset controller, instead the
reset lines for the various devices are integrated into the "BGR" (Bus
Gate / Reset) registers, for each device group: one for all UARTs, one
for all SPI interfaces, and so on.
The Allwinner CCU driver also doubles as a reset provider, and since the
reset lines are indeed just single bits in those BGR register, we can
represent them easily in an array of structs, just containing the
register offset and the bit number.
Add the location of the reset bits for all devices in the A523/T527
SoCs, using the existing sunxi CCU infrastructure.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://patch.msgid.link/20250307002628.10684-14-andre.przywara@arm.com
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c')
0 files changed, 0 insertions, 0 deletions