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| author | Chao Hao <chao.hao@mediatek.com> | 2020-07-03 07:41:26 +0300 |
|---|---|---|
| committer | Joerg Roedel <jroedel@suse.de> | 2020-07-10 17:13:11 +0300 |
| commit | 864444130eed304835b09c86a5bf2ff05bc2f4a2 (patch) | |
| tree | 7e77da511f06b82979e428ef541e907e63274c05 /drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | |
| parent | 829316b3bc897a3275a0354505fde3ccd0053936 (diff) | |
| download | linux-864444130eed304835b09c86a5bf2ff05bc2f4a2.tar.xz | |
iommu/mediatek: Modify MMU_CTRL register setting
The MMU_CTRL register of MT8173 is different from other SoCs.
The in_order_wr_en is bit[9] which is zero by default.
Other SoCs have the vitcim_tlb_en feature mapped to bit[12].
This bit is set to one by default. We need to preserve the bit
when setting F_MMU_TF_PROT_TO_PROGRAM_ADDR as otherwise the
bit will be cleared and IOMMU performance will drop.
Signed-off-by: Chao Hao <chao.hao@mediatek.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Cc: Matthias Brugger <matthias.bgg@gmail.com>
Cc: Yong Wu <yong.wu@mediatek.com>
Link: https://lore.kernel.org/r/20200703044127.27438-10-chao.hao@mediatek.com
Signed-off-by: Joerg Roedel <jroedel@suse.de>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c')
0 files changed, 0 insertions, 0 deletions