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| author | Chao Hao <chao.hao@mediatek.com> | 2020-07-03 07:41:21 +0300 |
|---|---|---|
| committer | Joerg Roedel <jroedel@suse.de> | 2020-07-10 17:13:10 +0300 |
| commit | 4bb2bf4c6ad36d5aef9fc7ecd01e89ae4f8d7ec7 (patch) | |
| tree | b93fc60a5f1c576f5556f64acacff470695fee4c /drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | |
| parent | 6b717796227ec8d4303adcdc574165d06e499f0f (diff) | |
| download | linux-4bb2bf4c6ad36d5aef9fc7ecd01e89ae4f8d7ec7.tar.xz | |
iommu/mediatek: Setting MISC_CTRL register
Add F_MMU_IN_ORDER_WR_EN_MASK and F_MMU_STANDARD_AXI_MODE_EN_MASK
definitions in MISC_CTRL register.
F_MMU_STANDARD_AXI_MODE_EN_MASK:
If we set F_MMU_STANDARD_AXI_MODE_EN_MASK (bit[3][19] = 0, not follow
standard AXI protocol), the iommu will priorize sending of urgent read
command over a normal read command. This improves the performance.
F_MMU_IN_ORDER_WR_EN_MASK:
If we set F_MMU_IN_ORDER_WR_EN_MASK (bit[1][17] = 0, out-of-order write),
the iommu will re-order write commands and send the write commands with
higher priority. Otherwise the sending of write commands will be done in
order. The feature is controlled by OUT_ORDER_WR_EN platform data flag.
Suggested-by: Yong Wu <yong.wu@mediatek.com>
Signed-off-by: Chao Hao <chao.hao@mediatek.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Cc: Matthias Brugger <matthias.bgg@gmail.com>
Link: https://lore.kernel.org/r/20200703044127.27438-5-chao.hao@mediatek.com
Signed-off-by: Joerg Roedel <jroedel@suse.de>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c')
0 files changed, 0 insertions, 0 deletions