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| author | Zong-Zhe Yang <kevin_yang@realtek.com> | 2023-05-08 11:43:34 +0300 |
|---|---|---|
| committer | Kalle Valo <kvalo@kernel.org> | 2023-05-11 16:19:50 +0300 |
| commit | 56617fd02adbf2ce7e18469895846ba82150cb1f (patch) | |
| tree | 887b799ac11b1eeee957d7dea902a707eab9b439 /drivers/fpga | |
| parent | aa70fa4f7dd80e4e495c30ff10a6c373c26902e0 (diff) | |
| download | linux-56617fd02adbf2ce7e18469895846ba82150cb1f.tar.xz | |
wifi: rtw89: ser: L1 add pre-M0 and post-M0 states
Newer FW re-design SER (syetem error recovery) L1 (level 1) flow.
New L1 flow will expect two extra states before original L1 flow.
* Before:
fw --- M1 --> driver
fw <-- M2 --- driver
fw --- M3 --> driver
fw <-- M4 --- driver
fw --- M5 --> driver
* After:
fw --- pre-M0 --> driver
fw <-- post-M0 --- driver
fw --- M1 --> driver
fw <-- M2 --- driver
fw --- M3 --> driver
fw <-- M4 --- driver
fw --- M5 --> driver
Then before M1, FW gets one more interval to deal with things that FW
should have handled well. To consider backward/forward compatibility,
FW and driver won't change flow from M1 to M5. (only except that halt
trigger control will change a little bit.) So, there will be two differnt
starting points of SER L1.
* old FW: SER L1 starts from M1
* new FW: SER L1 starts from pre-M0
Then, driver adds the new SER L1 entry and also keep the original one
instead of changing it.
Signed-off-by: Zong-Zhe Yang <kevin_yang@realtek.com>
Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Signed-off-by: Kalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20230508084335.42953-3-pkshih@realtek.com
Diffstat (limited to 'drivers/fpga')
0 files changed, 0 insertions, 0 deletions